[llvm] b84be9f - Add all constant physical registers to callee preserved masks
Alex Richardson via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 21 05:50:44 PDT 2022
Author: Alex Richardson
Date: 2022-09-21T12:50:12Z
New Revision: b84be9f2f1acb7229e4a4fa12e0832854c22bd57
URL: https://github.com/llvm/llvm-project/commit/b84be9f2f1acb7229e4a4fa12e0832854c22bd57
DIFF: https://github.com/llvm/llvm-project/commit/b84be9f2f1acb7229e4a4fa12e0832854c22bd57.diff
LOG: Add all constant physical registers to callee preserved masks
This allows MachineCopyPropagation to eliminate copies of constant registers
such as zero registers. They were previously not being eliminated as the
check for MO.clobbersPhysReg(AvailSrc) would return true for constant
registers such as MIPS $zero.
To avoid having to manually add the zero registers to all CalleeSavedRegs
instantiations in tablegen, I instead added a new isConstant bit to the
Register and set this for MIPS, RISC-V, and AArch64 zero registers.
RegisterInfoEmitter.cpp looks at this flag and adds all constant registers
to the preserved register mask.
This may also benefit other passes but so far I have only seen differences
in MachineCopyPropagation. In the future it might make sense to generate
`isConstantPhysReg()` from this information.
Original source: https://github.com/CTSRD-CHERI/llvm-project/commit/8588d8b81458ed6d87b674893e7752e6a6915574
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D131958
Added:
Modified:
llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
llvm/test/CodeGen/Mips/avoid-zero-copy.mir
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/utils/TableGen/RegisterInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir b/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
index 4558a1108d8fa..859be2d337476 100644
--- a/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
@@ -7,12 +7,11 @@
define i32 @foo() nounwind {
; ASM-LABEL: foo:
; ASM: // %bb.0:
- ; ASM-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+ ; ASM-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; ASM-NEXT: mov w0, wzr
- ; ASM-NEXT: mov w19, wzr
; ASM-NEXT: bl bar
- ; ASM-NEXT: mov w0, w19
- ; ASM-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+ ; ASM-NEXT: mov w0, wzr
+ ; ASM-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; ASM-NEXT: ret
call i32 @bar(i32 0)
ret i32 0
@@ -24,11 +23,10 @@ body: |
bb.0 (%ir-block.0):
; CHECK-LABEL: name: foo
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: renamable $w19 = COPY $wzr
; CHECK-NEXT: $w0 = COPY $wzr
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY killed renamable $w19
+ ; CHECK-NEXT: $w0 = COPY $wzr
; CHECK-NEXT: RET_ReallyLR implicit $w0
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
renamable $w19 = COPY $wzr
diff --git a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
index e617c7d91d9ad..5c7cffd109ea6 100644
--- a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
@@ -8,12 +8,9 @@
; ASM: # %bb.0:
; ASM-NEXT: daddiu $sp, $sp, -16
; ASM-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
- ; ASM-NEXT: sd $16, 0($sp) # 8-byte Folded Spill
- ; ASM-NEXT: move $16, $zero
; ASM-NEXT: jalr $25
; ASM-NEXT: move $4, $zero
- ; ASM-NEXT: move $4, $16
- ; ASM-NEXT: ld $16, 0($sp) # 8-byte Folded Reload
+ ; ASM-NEXT: move $4, $zero
; ASM-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; ASM-NEXT: jr $ra
; ASM-NEXT: daddiu $sp, $sp, 16
@@ -29,11 +26,10 @@ body: |
; CHECK: liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: renamable $s0_64 = COPY $zero_64
; CHECK-NEXT: $a0_64 = COPY $zero_64
; CHECK-NEXT: JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: $a0_64 = COPY killed renamable $s0_64
+ ; CHECK-NEXT: $a0_64 = COPY $zero_64
; CHECK-NEXT: PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
renamable $s0_64 = COPY $zero_64
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index d35b57b164b7e..0a38055718c74 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -650,7 +650,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfdi at plt
; RV32I-NEXT: mv s5, a1
-; RV32I-NEXT: mv a1, s2
+; RV32I-NEXT: li a1, 0
; RV32I-NEXT: bltz s6, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0
@@ -1436,7 +1436,7 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32I-NEXT: lui a3, 790016
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2 at plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv a0, s2
@@ -1749,7 +1749,7 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32I-NEXT: lui a3, 787968
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2 at plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv a0, s2
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 208a89ab5549a..971ebb710af23 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1665,6 +1665,15 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
}
+ // Add all constant physical registers to the preserved mask:
+ SetTheory::RecSet ConstantSet;
+ for (auto &Reg : RegBank.getRegisters()) {
+ if (Reg.Constant)
+ ConstantSet.insert(Reg.TheDef);
+ }
+ Covered |= RegBank.computeCoveredRegisters(
+ ArrayRef<Record *>(ConstantSet.begin(), ConstantSet.end()));
+
OS << "static const uint32_t " << CSRSet->getName()
<< "_RegMask[] = { ";
printBitVectorAsHex(OS, Covered, 32);
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