[PATCH] D134257: [WebAssembly] Improve codegen for loading scalars from memory to v128

[Fanchen Kong via Phabricator via llvm-commits]

fanchenkong1 added a comment.

Thanks Thomas for reviewing this change!



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Comment at: llvm/test/CodeGen/WebAssembly/simd-offset.ll:1196-1199
+; CHECK-NEXT:    i32.const 24
+; CHECK-NEXT:    i32x4.shl
+; CHECK-NEXT:    i32.const 24
+; CHECK-NEXT:    i32x4.shr_s
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tlively wrote:
> It looks like there is some room for improvement here. These shifts aren't necessary, are they? It would be good to at least add a TODO about cleaning them up.
Yes, a TODO can be added if further change is needed. But I'm not sure if I fully understand what to do to remove the shifts. Does it mean by using two sign extend? e.g.
  i16x8.extend_low_i8x16_s
  i32x4.extend_low_i16x8_s


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Comment at: llvm/test/CodeGen/WebAssembly/simd-offset.ll:1210
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    v128.const 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    local.get 0
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tlively wrote:
> Do you know why the zero vector is materialized here while the previous function uses a `local.get` to get an implicit zero vector?
The difference seems to be introduced by the vector legalizer, where the sign extend is expanded by VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG, followed with VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG. The later one may introduce an undef node. While the zero extend is expanded by VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG, where an explicit zero vector is created.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134257/new/

https://reviews.llvm.org/D134257