[llvm] 230dbe0 - VE: Use generated checks for a copy-pasted output test
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 20 13:51:13 PDT 2022
Author: Matt Arsenault
Date: 2022-09-20T16:51:04-04:00
New Revision: 230dbe085788678d594a0f908cae1a7eaa6f5408
URL: https://github.com/llvm/llvm-project/commit/230dbe085788678d594a0f908cae1a7eaa6f5408
DIFF: https://github.com/llvm/llvm-project/commit/230dbe085788678d594a0f908cae1a7eaa6f5408.diff
LOG: VE: Use generated checks for a copy-pasted output test
Added:
Modified:
llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll b/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
index 43b33866889f2..5a4da1a4a4976 100644
--- a/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
+++ b/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve | FileCheck %s
;;; Test atomic compare and exchange weak for all types and all memory order
@@ -95,12 +96,12 @@ define zeroext i1 @_Z26atomic_cmp_swap_relaxed_i1RNSt3__16atomicIbEERbb(%"struct
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = zext i1 %2 to i8
@@ -139,12 +140,12 @@ define signext i8 @_Z26atomic_cmp_swap_relaxed_i8RNSt3__16atomicIcEERcc(%"struct
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -182,12 +183,12 @@ define zeroext i8 @_Z26atomic_cmp_swap_relaxed_u8RNSt3__16atomicIhEERhh(%"struct
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -226,12 +227,12 @@ define signext i16 @_Z27atomic_cmp_swap_relaxed_i16RNSt3__16atomicIsEERss(%"stru
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB3_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -269,12 +270,12 @@ define zeroext i16 @_Z27atomic_cmp_swap_relaxed_u16RNSt3__16atomicItEERtt(%"stru
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s5
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -302,10 +303,10 @@ define signext i32 @_Z27atomic_cmp_swap_relaxed_i32RNSt3__16atomicIiEERii(%"stru
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB5_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -333,10 +334,10 @@ define zeroext i32 @_Z27atomic_cmp_swap_relaxed_u32RNSt3__16atomicIjEERjj(%"stru
; CHECK-NEXT: cmps.w.sx %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -364,10 +365,10 @@ define i64 @_Z27atomic_cmp_swap_relaxed_i64RNSt3__16atomicIlEERll(%"struct.std::
; CHECK-NEXT: cmps.l %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -395,10 +396,10 @@ define i64 @_Z27atomic_cmp_swap_relaxed_u64RNSt3__16atomicImEERmm(%"struct.std::
; CHECK-NEXT: cmps.l %s4, %s2, %s3
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -420,7 +421,22 @@ define i64 @_Z27atomic_cmp_swap_relaxed_u64RNSt3__16atomicImEERmm(%"struct.std::
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_relaxed_i128RNSt3__16atomicInEERnn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_relaxed_i128RNSt3__16atomicInEERnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
@@ -436,6 +452,9 @@ define i128 @_Z28atomic_cmp_swap_relaxed_i128RNSt3__16atomicInEERnn(%"struct.std
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
@@ -451,7 +470,22 @@ define i128 @_Z28atomic_cmp_swap_relaxed_i128RNSt3__16atomicInEERnn(%"struct.std
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_relaxed_u128RNSt3__16atomicIoEERoo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_relaxed_u128RNSt3__16atomicIoEERoo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB10_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
@@ -467,6 +501,9 @@ define i128 @_Z28atomic_cmp_swap_relaxed_u128RNSt3__16atomicIoEERoo(%"struct.std
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
@@ -499,12 +536,12 @@ define zeroext i1 @_Z26atomic_cmp_swap_acquire_i1RNSt3__16atomicIbEERbb(%"struct
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = zext i1 %2 to i8
@@ -544,12 +581,12 @@ define signext i8 @_Z26atomic_cmp_swap_acquire_i8RNSt3__16atomicIcEERcc(%"struct
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -588,12 +625,12 @@ define zeroext i8 @_Z26atomic_cmp_swap_acquire_u8RNSt3__16atomicIhEERhh(%"struct
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB13_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -633,12 +670,12 @@ define signext i16 @_Z27atomic_cmp_swap_acquire_i16RNSt3__16atomicIsEERss(%"stru
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB14_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB14_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -677,12 +714,12 @@ define zeroext i16 @_Z27atomic_cmp_swap_acquire_u16RNSt3__16atomicItEERtt(%"stru
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB15_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB15_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -711,10 +748,10 @@ define signext i32 @_Z27atomic_cmp_swap_acquire_i32RNSt3__16atomicIiEERii(%"stru
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB16_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB16_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -743,10 +780,10 @@ define zeroext i32 @_Z27atomic_cmp_swap_acquire_u32RNSt3__16atomicIjEERjj(%"stru
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB17_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -775,10 +812,10 @@ define i64 @_Z27atomic_cmp_swap_acquire_i64RNSt3__16atomicIlEERll(%"struct.std::
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB18_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB18_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -807,10 +844,10 @@ define i64 @_Z27atomic_cmp_swap_acquire_u64RNSt3__16atomicImEERmm(%"struct.std::
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 2
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB19_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB19_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -832,7 +869,22 @@ define i64 @_Z27atomic_cmp_swap_acquire_u64RNSt3__16atomicImEERmm(%"struct.std::
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_acquire_i128RNSt3__16atomicInEERnn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_acquire_i128RNSt3__16atomicInEERnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB20_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB20_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
@@ -848,6 +900,9 @@ define i128 @_Z28atomic_cmp_swap_acquire_i128RNSt3__16atomicInEERnn(%"struct.std
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
@@ -863,7 +918,22 @@ define i128 @_Z28atomic_cmp_swap_acquire_i128RNSt3__16atomicInEERnn(%"struct.std
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_acquire_u128RNSt3__16atomicIoEERoo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_acquire_u128RNSt3__16atomicIoEERoo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB21_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
@@ -879,6 +949,9 @@ define i128 @_Z28atomic_cmp_swap_acquire_u128RNSt3__16atomicIoEERoo(%"struct.std
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
@@ -912,12 +985,12 @@ define zeroext i1 @_Z26atomic_cmp_swap_seq_cst_i1RNSt3__16atomicIbEERbb(%"struct
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB22_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB22_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = zext i1 %2 to i8
@@ -958,12 +1031,12 @@ define signext i8 @_Z26atomic_cmp_swap_seq_cst_i8RNSt3__16atomicIcEERcc(%"struct
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB23_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB23_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1003,12 +1076,12 @@ define zeroext i8 @_Z26atomic_cmp_swap_seq_cst_u8RNSt3__16atomicIhEERhh(%"struct
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st1b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB24_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1049,12 +1122,12 @@ define signext i16 @_Z27atomic_cmp_swap_seq_cst_i16RNSt3__16atomicIsEERss(%"stru
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1094,12 +1167,12 @@ define zeroext i16 @_Z27atomic_cmp_swap_seq_cst_u16RNSt3__16atomicItEERtt(%"stru
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s3, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s5, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s5, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: srl %s0, %s2, %s0
; CHECK-NEXT: st2b %s0, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1129,10 +1202,10 @@ define signext i32 @_Z27atomic_cmp_swap_seq_cst_i32RNSt3__16atomicIiEERii(%"stru
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB27_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1162,10 +1235,10 @@ define zeroext i32 @_Z27atomic_cmp_swap_seq_cst_u32RNSt3__16atomicIjEERjj(%"stru
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.w %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s2, %s3, .LBB28_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB28_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1195,10 +1268,10 @@ define i64 @_Z27atomic_cmp_swap_seq_cst_i64RNSt3__16atomicIlEERll(%"struct.std::
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB29_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB29_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1228,10 +1301,10 @@ define i64 @_Z27atomic_cmp_swap_seq_cst_u64RNSt3__16atomicImEERmm(%"struct.std::
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s4
; CHECK-NEXT: fencem 3
-; CHECK-NEXT: breq.l %s2, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s2, %s3, .LBB30_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s2, (, %s1)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB30_2:
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%4 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
@@ -1253,7 +1326,22 @@ define i64 @_Z27atomic_cmp_swap_seq_cst_u64RNSt3__16atomicImEERmm(%"struct.std::
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_seq_cst_i128RNSt3__16atomicInEERnn(%"struct.std::__1::atomic.40"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_seq_cst_i128RNSt3__16atomicInEERnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB31_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
@@ -1269,6 +1357,9 @@ define i128 @_Z28atomic_cmp_swap_seq_cst_i128RNSt3__16atomicInEERnn(%"struct.std
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
@@ -1284,7 +1375,22 @@ define i128 @_Z28atomic_cmp_swap_seq_cst_i128RNSt3__16atomicInEERnn(%"struct.std
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_cmp_swap_seq_cst_u128RNSt3__16atomicIoEERoo(%"struct.std::__1::atomic.45"* nonnull align 16 dereferenceable(16) %0, i128* nonnull align 16 dereferenceable(16) %1, i128 %2) {
; CHECK-LABEL: _Z28atomic_cmp_swap_seq_cst_u128RNSt3__16atomicIoEERoo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB32_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: or %s6, 0, %s1
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: st %s3, 248(, %s11)
@@ -1300,6 +1406,9 @@ define i128 @_Z28atomic_cmp_swap_seq_cst_u128RNSt3__16atomicIoEERoo(%"struct.std
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%4 = alloca i128, align 16
%5 = bitcast i128* %4 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %5)
@@ -1315,7 +1424,19 @@ define i128 @_Z28atomic_cmp_swap_seq_cst_u128RNSt3__16atomicIoEERoo(%"struct.std
; Function Attrs: nofree nounwind mustprogress
define zeroext i1 @_Z30atomic_cmp_swap_relaxed_stk_i1Rbb(i8* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_i1Rbb:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB33_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB33_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld1b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: lea %s4, -256
@@ -1327,10 +1448,10 @@ define zeroext i1 @_Z30atomic_cmp_swap_relaxed_stk_i1Rbb(i8* nocapture nonnull a
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB33_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1362,7 +1483,19 @@ declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
; Function Attrs: nofree nounwind mustprogress
define signext i8 @_Z30atomic_cmp_swap_relaxed_stk_i8Rcc(i8* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_i8Rcc:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB34_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB34_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld1b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: and %s1, %s1, (56)0
@@ -1375,10 +1508,10 @@ define signext i8 @_Z30atomic_cmp_swap_relaxed_stk_i8Rcc(i8* nocapture nonnull a
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1404,7 +1537,19 @@ define signext i8 @_Z30atomic_cmp_swap_relaxed_stk_i8Rcc(i8* nocapture nonnull a
; Function Attrs: nofree nounwind mustprogress
define zeroext i8 @_Z30atomic_cmp_swap_relaxed_stk_u8Rhh(i8* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_u8Rhh:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB35_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB35_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld1b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: lea %s4, -256
@@ -1416,10 +1561,10 @@ define zeroext i8 @_Z30atomic_cmp_swap_relaxed_stk_u8Rhh(i8* nocapture nonnull a
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB35_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1445,7 +1590,19 @@ define zeroext i8 @_Z30atomic_cmp_swap_relaxed_stk_u8Rhh(i8* nocapture nonnull a
; Function Attrs: nofree nounwind mustprogress
define signext i16 @_Z31atomic_cmp_swap_relaxed_stk_i16Rss(i16* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i16Rss:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB36_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB36_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld2b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: and %s1, %s1, (48)0
@@ -1458,10 +1615,10 @@ define signext i16 @_Z31atomic_cmp_swap_relaxed_stk_i16Rss(i16* nocapture nonnul
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB36_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB36_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1488,7 +1645,19 @@ define signext i16 @_Z31atomic_cmp_swap_relaxed_stk_i16Rss(i16* nocapture nonnul
; Function Attrs: nofree nounwind mustprogress
define zeroext i16 @_Z31atomic_cmp_swap_relaxed_stk_u16Rtt(i16* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u16Rtt:
-; CHECK: .LBB{{[0-9]+}}_4: # %partword.cmpxchg.loop
+; CHECK: # %bb.0: # %partword.cmpxchg.loop
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB37_4
+; CHECK-NEXT: # %bb.3: # %partword.cmpxchg.loop
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB37_4: # %partword.cmpxchg.loop
; CHECK-NEXT: ld2b.zx %s2, (, %s0)
; CHECK-NEXT: ldl.zx %s3, 8(, %s11)
; CHECK-NEXT: lea %s4, -65536
@@ -1500,10 +1669,10 @@ define zeroext i16 @_Z31atomic_cmp_swap_relaxed_stk_u16Rtt(i16* nocapture nonnul
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB37_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1530,16 +1699,28 @@ define zeroext i16 @_Z31atomic_cmp_swap_relaxed_stk_u16Rtt(i16* nocapture nonnul
; Function Attrs: nofree nounwind mustprogress
define signext i32 @_Z31atomic_cmp_swap_relaxed_stk_i32Rii(i32* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i32Rii:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB38_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB38_4:
; CHECK-NEXT: ldl.sx %s3, (, %s0)
; CHECK-NEXT: cas.w %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB38_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1566,16 +1747,28 @@ define signext i32 @_Z31atomic_cmp_swap_relaxed_stk_i32Rii(i32* nocapture nonnul
; Function Attrs: nofree nounwind mustprogress
define zeroext i32 @_Z31atomic_cmp_swap_relaxed_stk_u32Rjj(i32* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u32Rjj:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB39_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB39_4:
; CHECK-NEXT: ldl.sx %s3, (, %s0)
; CHECK-NEXT: cas.w %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB39_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB39_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1602,16 +1795,28 @@ define zeroext i32 @_Z31atomic_cmp_swap_relaxed_stk_u32Rjj(i32* nocapture nonnul
; Function Attrs: nofree nounwind mustprogress
define i64 @_Z31atomic_cmp_swap_relaxed_stk_i64Rll(i64* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i64Rll:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB40_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB40_4:
; CHECK-NEXT: ld %s3, (, %s0)
; CHECK-NEXT: cas.l %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB40_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB40_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1638,16 +1843,28 @@ define i64 @_Z31atomic_cmp_swap_relaxed_stk_i64Rll(i64* nocapture nonnull align
; Function Attrs: nofree nounwind mustprogress
define i64 @_Z31atomic_cmp_swap_relaxed_stk_u64Rmm(i64* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u64Rmm:
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l %s11, %s8, .LBB41_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB41_4:
; CHECK-NEXT: ld %s3, (, %s0)
; CHECK-NEXT: cas.l %s1, 8(%s11), %s3
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB41_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
; CHECK-NEXT: b.l.t (, %s10)
@@ -1674,7 +1891,22 @@ define i64 @_Z31atomic_cmp_swap_relaxed_stk_u64Rmm(i64* nocapture nonnull align
; Function Attrs: nounwind mustprogress
define i128 @_Z32atomic_cmp_swap_relaxed_stk_i128Rnn(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z32atomic_cmp_swap_relaxed_stk_i128Rnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB42_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB42_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -1690,6 +1922,9 @@ define i128 @_Z32atomic_cmp_swap_relaxed_stk_i128Rnn(i128* nonnull align 16 dere
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca %"struct.std::__1::atomic.40", align 16
%5 = bitcast %"struct.std::__1::atomic.40"* %4 to i8*
@@ -1708,7 +1943,22 @@ define i128 @_Z32atomic_cmp_swap_relaxed_stk_i128Rnn(i128* nonnull align 16 dere
; Function Attrs: nounwind mustprogress
define i128 @_Z32atomic_cmp_swap_relaxed_stk_u128Roo(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z32atomic_cmp_swap_relaxed_stk_u128Roo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB43_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB43_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -1724,6 +1974,9 @@ define i128 @_Z32atomic_cmp_swap_relaxed_stk_u128Roo(i128* nonnull align 16 dere
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca %"struct.std::__1::atomic.45", align 16
%5 = bitcast %"struct.std::__1::atomic.45"* %4 to i8*
@@ -1760,10 +2013,10 @@ define zeroext i1 @_Z29atomic_cmp_swap_relaxed_gv_i1Rbb(i8* nocapture nonnull al
; CHECK-NEXT: cmps.w.sx %s3, %s2, %s3
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s1, .LBB44_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s2, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB44_2:
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8
@@ -1803,10 +2056,10 @@ define signext i8 @_Z29atomic_cmp_swap_relaxed_gv_i8Rcc(i8* nocapture nonnull al
; CHECK-NEXT: cmps.w.sx %s2, %s3, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s2
-; CHECK-NEXT: brne.w 0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s1, .LBB45_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s3, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB45_2:
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i8, i8* %0, align 1
@@ -1845,10 +2098,10 @@ define zeroext i8 @_Z29atomic_cmp_swap_relaxed_gv_u8Rhh(i8* nocapture nonnull al
; CHECK-NEXT: cmps.w.sx %s3, %s2, %s3
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s1, .LBB46_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st1b %s2, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB46_2:
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i8, i8* %0, align 1
@@ -1885,10 +2138,10 @@ define signext i16 @_Z30atomic_cmp_swap_relaxed_gv_i16Rss(i16* nocapture nonnull
; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s2, .LBB47_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB47_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i16, i16* %0, align 2
@@ -1924,10 +2177,10 @@ define zeroext i16 @_Z30atomic_cmp_swap_relaxed_gv_u16Rtt(i16* nocapture nonnull
; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3
-; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s2, .LBB48_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB48_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i16, i16* %0, align 2
@@ -1957,10 +2210,10 @@ define signext i32 @_Z30atomic_cmp_swap_relaxed_gv_i32Rii(i32* nocapture nonnull
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB49_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i32, i32* %0, align 4
@@ -1990,10 +2243,10 @@ define zeroext i32 @_Z30atomic_cmp_swap_relaxed_gv_u32Rjj(i32* nocapture nonnull
; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.w %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w %s1, %s3, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: stl %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i32, i32* %0, align 4
@@ -2023,10 +2276,10 @@ define i64 @_Z30atomic_cmp_swap_relaxed_gv_i64Rll(i64* nocapture nonnull align 8
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB51_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB51_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i64, i64* %0, align 8
@@ -2056,10 +2309,10 @@ define i64 @_Z30atomic_cmp_swap_relaxed_gv_u64Rmm(i64* nocapture nonnull align 8
; CHECK-NEXT: cmps.l %s4, %s1, %s3
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4
-; CHECK-NEXT: breq.l %s1, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.l %s1, %s3, .LBB52_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: st %s1, (, %s0)
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB52_2:
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%3 = load i64, i64* %0, align 8
@@ -2080,7 +2333,22 @@ define i64 @_Z30atomic_cmp_swap_relaxed_gv_u64Rmm(i64* nocapture nonnull align 8
; Function Attrs: nounwind mustprogress
define i128 @_Z31atomic_cmp_swap_relaxed_gv_i128Rnn(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_gv_i128Rnn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB53_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB53_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
@@ -2098,6 +2366,9 @@ define i128 @_Z31atomic_cmp_swap_relaxed_gv_i128Rnn(i128* nonnull align 16 deref
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
@@ -2112,7 +2383,22 @@ define i128 @_Z31atomic_cmp_swap_relaxed_gv_i128Rnn(i128* nonnull align 16 deref
; Function Attrs: nounwind mustprogress
define i128 @_Z31atomic_cmp_swap_relaxed_gv_u128Roo(i128* nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_gv_u128Roo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -256(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB54_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB54_2:
; CHECK-NEXT: or %s6, 0, %s0
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
@@ -2130,6 +2416,9 @@ define i128 @_Z31atomic_cmp_swap_relaxed_gv_u128Roo(i128* nonnull align 16 deref
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = bitcast i128* %3 to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %4)
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