[PATCH] D125657: [RegisterCoalescer] fix dst subreg replacement during remat copy trick

Tue Sep 20 07:29:29 PDT 2022

ivafanas added a comment.

In D125657#3801453 <https://reviews.llvm.org/D125657#3801453>, @qcolombet wrote:

> Hi @ivafanas,
>
> Any chance you can provide a test case with the patch?
> In particular, I'd like to confirm how we end up in this situation. (I suppose we have a copy that fed back to a phi?)
>
> For the record, I believe this problem has been here for ages, because trivial rematerialization has been limited to instruction with no operands for the most part. Put differently, I'm not surprised you're running into bugs like this.
> I'm actually surprised your instruction is trivially rematerializable to begin with.
>
> Cheers,
> -Quentin

Hi @qcolombet ,

We have triggered the issue on the custom out-of-tree architecture with predicated execution. That's why I can not provide a test case, unfortunately.
There is a common scenario for instruction to have the same register defined and "undef" used as operand.

Something like:

  %2 = ADD %0, %1, undef %2, $sprf0, 0

Or

  %1 = MOV 123, undef %1, $sprf0, 0

I've done my best to explain the problem in patch description and comment :) Don't know how to explain it better)

I'm not familiar with other architectures, but having in mind that the code exists for years and nobody triggered the issue, seems like it is not the case for other architectures.
Maybe it is ok that patch will live only in our fork, I'm not sure.

Repository:
  rG LLVM Github Monorepo

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