[llvm] 0015ede - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-09-20T14:24:07+01:00
New Revision: 0015edeefd74ba331c328ddfb0ad32774ce90030

URL: https://github.com/llvm/llvm-project/commit/0015edeefd74ba331c328ddfb0ad32774ce90030
DIFF: https://github.com/llvm/llvm-project/commit/0015edeefd74ba331c328ddfb0ad32774ce90030.diff

LOG: Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index c9b1572ccaa9..3f87cff12bc0 100755
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -2520,7 +2520,7 @@ HexagonTargetLowering::ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const {
   auto [Frac, Ovf] = emitHvxShiftRightRnd(Frac0, ExpWidth + 1, false, DAG);
   if (Signed) {
     SDValue IsNeg = DAG.getSetCC(dl, PredTy, Op0, Zero, ISD::SETLT);
-    SDValue M80 = DAG.getConstant(1 << (ElemWidth - 1), dl, InpTy);
+    SDValue M80 = DAG.getConstant(1ull << (ElemWidth - 1), dl, InpTy);
     SDValue Sign = DAG.getNode(ISD::VSELECT, dl, InpTy, {IsNeg, M80, Zero});
     Frac = DAG.getNode(ISD::OR, dl, InpTy, {Sign, Frac});
   }