[PATCH] D134061: [RISCV] Custom legalize splat_vector and disable unprofitable generic DAG combine

Paul Walker via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 20 04:59:09 PDT 2022


paulwalker-arm added a comment.

Are you able to write tests that show the value of removing the combine for riscv? because the current ones don't highlight much. In general it seems good to simplify splat operations as subvector operations get in the way of other combines as well as isel (things like matching immediate operands).

>From an AArch64 specific point of view these extracts are normally removed after operation legalisation (where for AArch64/SVE fixed length vectors are lowered to scalable vectors) when you end up with extract/insert subvector pairs.  The problematic case is i1 fixed length vectors which are not type legal and hence the combine is necessary to catch those cases.

I've no objection to making this combine target specific but it does seem like something that is generically good and without seeing the exact problem it is hard to suggest an alternative.


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