[PATCH] D133484: [AArch64][SVE] Fix AArch64_SVE_VectorCall calling convention

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 461526.
MattDevereau added a comment.

I've simplified the pointless `if(A && B || A)` check. This was leftover from when I copied and simplified the code from `AArch64TargetLowering::LowerFormalArguments` which has seperate logic for predicates and scalable vectors like so:

  if (VA.isRegLoc()) {
    // Arguments stored in registers.
    EVT RegVT = VA.getLocVT();
    const TargetRegisterClass *RC;
  
    if (RegVT == MVT::i32)
      RC = &AArch64::GPR32RegClass;
    else if (RegVT == MVT::i64)
      RC = &AArch64::GPR64RegClass;
    else if (RegVT == MVT::f16 || RegVT == MVT::bf16)
      RC = &AArch64::FPR16RegClass;
    else if (RegVT == MVT::f32)
      RC = &AArch64::FPR32RegClass;
    else if (RegVT == MVT::f64 || RegVT.is64BitVector())
      RC = &AArch64::FPR64RegClass;
    else if (RegVT == MVT::f128 || RegVT.is128BitVector())
      RC = &AArch64::FPR128RegClass;
    else if (RegVT.isScalableVector() &&
             RegVT.getVectorElementType() == MVT::i1) {
      FuncInfo->setIsSVECC(true);
      RC = &AArch64::PPRRegClass;
    } else if (RegVT.isScalableVector()) {
      FuncInfo->setIsSVECC(true);
      RC = &AArch64::ZPRRegClass;
    } else
      llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133484/new/

https://reviews.llvm.org/D133484

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

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