[PATCH] D134228: [RISCV] Massage debug loc to improve scheduling of addressing for scatter/gather

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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This patch is admittedly a bit of a hack, but it's a useful hack.

SelectionDAG likes to build scaled scatter/gather nodes.  RISCV doesn't support scaling, so we have a combine which unfolds this.  However, the newly unfolded scaling inherits the memory ops debug location, not the debug location of the original GEP (which no longer exists).  As a result, DAG schedule tends to mix the scaling with any e.g. interleaved scatter/gathers.  This is bad because the addressing is often in a different data width than the scatter/gather and thus requires a bunch of extra vsetvli toggles.

We probably should prevent SelectionDAGBuilder from forming these at all, and I intend to play with that a bit to see if it's straight forward.  However, this is an improvement on the current codegen at minimal cost, so I think we should take the workaround for the moment.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134228

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

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