[llvm] 2e74157 - [RISCV]Preserve (and X, 0xffff) in targetShrinkDemandedConstant

[via llvm-commits]

Author: LiaoChunyu
Date: 2022-09-19T14:19:38+08:00
New Revision: 2e74157ad47b18959ac03e0e5000cd0a15fe76e0

URL: https://github.com/llvm/llvm-project/commit/2e74157ad47b18959ac03e0e5000cd0a15fe76e0
DIFF: https://github.com/llvm/llvm-project/commit/2e74157ad47b18959ac03e0e5000cd0a15fe76e0.diff

LOG: [RISCV]Preserve (and X, 0xffff) in targetShrinkDemandedConstant

shrinkdemandedconstant does some optimizations, but is not very friendly to riscv, targetShrinkDemandedConstant to limit the damage.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134155

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ff9993bcb9e2c..9c9b76012e9a2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10041,12 +10041,11 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant(
 
   // And has a few special cases for zext.
   if (Opcode == ISD::AND) {
-    // Preserve (and X, 0xffff) when zext.h is supported.
-    if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) {
-      APInt NewMask = APInt(Mask.getBitWidth(), 0xffff);
-      if (IsLegalMask(NewMask))
-        return UseMask(NewMask);
-    }
+    // Preserve (and X, 0xffff), if zext.h exists use zext.h,
+    // otherwise use SLLI + SRLI.
+    APInt NewMask = APInt(Mask.getBitWidth(), 0xffff);
+    if (IsLegalMask(NewMask))
+      return UseMask(NewMask);
 
     // Try to preserve (and X, 0xffffffff), the (zext_inreg X, i32) pattern.
     if (VT == MVT::i64) {

diff  --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
index 90c982ec0b9e4..24b5bc3221b65 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -140,3 +140,16 @@ define signext i32 @andi_srliw(i32 signext %0, ptr %1, i32 signext %2) {
   %6 = add i32 %4, %2
   ret i32 %6
 }
+
+define i32 @and_or(i32 signext %x) {
+; CHECK-LABEL: and_or:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ori a0, a0, 255
+; CHECK-NEXT:    slli a0, a0, 48
+; CHECK-NEXT:    srli a0, a0, 48
+; CHECK-NEXT:    ret
+entry:
+  %and = and i32 %x, 65280
+  %or = or i32 %and, 255
+  ret i32 %or
+}