[PATCH] D134155: [RISCV]Preserve (and X, 0xffff) in targetShrinkDemandedConstant

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10045
   if (Opcode == ISD::AND) {
-    // Preserve (and X, 0xffff) when zext.h is supported.
-    if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) {
-      APInt NewMask = APInt(Mask.getBitWidth(), 0xffff);
-      if (IsLegalMask(NewMask))
-        return UseMask(NewMask);
-    }
+    // Preserve (and X, 0xffff), if zext.h exists use zext.h,
+    // otherwise use SLLI + SRLI.
----------------
craig.topper wrote:
> liaolucy wrote:
> > I'm actually not sure if there are side effects. 
> > 
> > I also implemented a version in RISCV DAGcombine, maybe it can be used as an alternative
> What does the DAGCombine do? When it get in an infinite loop with shrinkDemandedConstant?

Current implementation:
```
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1d5cd3ecd8ea..a6a764c2032b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8630,6 +8630,25 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;

+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+  // fold (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 
+  auto *C1 = dyn_cast<ConstantSDNode>(N1);
+  if (C1 && N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
+    if (auto *C2 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+      const APInt &ImmC1 = C1->getAPIntValue();
+      const APInt &ImmC2 = C2->getAPIntValue();
+      const APInt &ImmC = ImmC1|ImmC2;
+      unsigned MinSignedBits = ImmC.getMinSignedBits();
+      if (MinSignedBits <= 12) {
+      EVT VT = N->getValueType(0);
+      SDValue NewOR = DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);
+      SDValue NewN1 = DAG.getConstant(ImmC1|ImmC2, SDLoc(N), VT);
+      return DAG.getNode(ISD::AND, SDLoc(N), VT, NewOR, NewN1);
+      }
+    } 
+  }
+
   // fold (or (select cond, 0, y), x) ->
   //      (select cond, x, (or x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134155/new/

https://reviews.llvm.org/D134155