[llvm] 930315f - [AMDGPU] Fix isSGPRReg for special registers

[Carl Ritson via llvm-commits]

Author: Carl Ritson
Date: 2022-09-19T08:49:43+09:00
New Revision: 930315f6aa587ac962183708844eb2390d5ba55e

URL: https://github.com/llvm/llvm-project/commit/930315f6aa587ac962183708844eb2390d5ba55e
DIFF: https://github.com/llvm/llvm-project/commit/930315f6aa587ac962183708844eb2390d5ba55e.diff

LOG: [AMDGPU] Fix isSGPRReg for special registers

Special registers, e.g. MODE, do not have register classes so
will cause null pointer exception if passed to isSGPRReg.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D134025

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 15edf7c07dd1e..218fa274586ef 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2696,7 +2696,7 @@ bool SIRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI,
     RC = MRI.getRegClass(Reg);
   else
     RC = getPhysRegClass(Reg);
-  return isSGPRClass(RC);
+  return RC ? isSGPRClass(RC) : false;
 }
 
 const TargetRegisterClass *