[PATCH] D134075: [Lanai] Fix useDeprecatedPositionallyEncodedOperands errors.
James Y Knight via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 16 13:55:16 PDT 2022
jyknight created this revision.
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This is a follow-on to https://reviews.llvm.org/D134073.
Lanai was almost clean: the only issue is that 'bit' behaves
differently than 'bits<1>', because only the 'bits' type preserves
unresolved references via 'keepUnsetBits()' in
TableGen/Record.h. Thus, use bits instead.
This issue _would_ have caused invalid instruction emission/decoding,
except that the PQ bits were being overriden after the fact by code in
'adjustPqBits' in MCTargetDesc/LanaiMCCodeEmitter.cpp, and
'PostOperandDecodeAdjust' in Disassembler/LanaiDisassembler.cpp.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D134075
Files:
llvm/lib/Target/Lanai/Lanai.td
llvm/lib/Target/Lanai/LanaiInstrFormats.td
Index: llvm/lib/Target/Lanai/LanaiInstrFormats.td
===================================================================
--- llvm/lib/Target/Lanai/LanaiInstrFormats.td
+++ llvm/lib/Target/Lanai/LanaiInstrFormats.td
@@ -197,8 +197,8 @@
: InstLanai<outs, ins, asmstr, pattern> {
bits<5> Rd;
bits<5> Rs1;
- bit P;
- bit Q;
+ bits<1> P;
+ bits<1> Q;
bits<16> imm16;
// Dummy variables to allow multiclass definition of RM and RRM
bits<2> YL;
@@ -259,8 +259,8 @@
bits<5> Rd;
bits<5> Rs1;
bits<5> Rs2;
- bit P;
- bit Q;
+ bits<1> P;
+ bits<1> Q;
bits<3> BBB;
bits<5> JJJJJ;
bits<2> YL;
@@ -504,8 +504,8 @@
bit Y;
bit S;
bit E;
- bit P;
- bit Q;
+ bits<1> P;
+ bits<1> Q;
bits<10> imm10;
let Opcode = 0b1111;
Index: llvm/lib/Target/Lanai/Lanai.td
===================================================================
--- llvm/lib/Target/Lanai/Lanai.td
+++ llvm/lib/Target/Lanai/Lanai.td
@@ -21,9 +21,7 @@
include "LanaiCallingConv.td"
include "LanaiInstrInfo.td"
-def LanaiInstrInfo : InstrInfo {
- let useDeprecatedPositionallyEncodedOperands = 1;
-}
+def LanaiInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// Lanai processors supported.
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