[PATCH] D134073: [TableGen] Add useDeprecatedPositionallyEncodedOperands option.

[James Y Knight via Phabricator via llvm-commits]

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The existing undefined-bitfield-to-operand matching behavior is very
hard to understand, due to the combination of positional and named
matching. This can make it difficult to track down a bug in a target's
instruction definitions.

Over the last decade, folks have tried to work-around this in various
ways, but it's time to finally ditch the positional matching. With
https://reviews.llvm.org/D131003, there are no longer cases that
_require_ positional matching, and it's time to start removing usage
and support for it.

Therefore: add a (default-false) option, and set it to true only in
those targets that require positional matching today. Subsequent
changes will start cleaning up additional in-tree targets.

NOTE TO OUT OF TREE TARGET MAINTAINERS:

If this change breaks your build, you may restore the previous
behavior simply by adding:

  let useDeprecatedPositionallyEncodedOperands = 1;

to your target's InstrInfo tablegen definition. However, this is
temporary -- the option will be removed in the future.

If your target does not set 'decodePositionallyEncodedOperands', you
may thus start migrating to named operands. However, if you _do_
currently set that option, I recommend waiting until a subsequent
change lands, which adds decoder support for named sub-operands.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134073

Files:
  llvm/include/llvm/Target/Target.td
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/R600.td
  llvm/lib/Target/AVR/AVR.td
  llvm/lib/Target/Lanai/Lanai.td
  llvm/lib/Target/Mips/Mips.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/Sparc/Sparc.td
  llvm/lib/Target/VE/VE.td
  llvm/test/TableGen/InsufficientPositionalOperands.td
  llvm/utils/TableGen/CodeEmitterGen.cpp
  llvm/utils/TableGen/DecoderEmitter.cpp

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