[PATCH] D134061: [RISCV] Custom legalize splat_vector and disable unprofitable generic DAG combine

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added reviewers: craig.topper, paulwalker-arm, cameron.mcinally.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, ecnelises, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, asb, hiraditya, kristof.beyls, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

The motivation of this patch is reduce the number of unique ways we handle splats in the RISCV backend.  Before this, we would expand the splat vector into a build_vector for generic IR, but for intrinsics we'd frequently end up emitting a splat_vector during lowering and rely on later legalization.  This meant that depending on the exact test case you looked at, very similar splats could take divergent paths during ISEL.

This change includes effectively a revert of D120328 <https://reviews.llvm.org/D120328>.  This transformation is not generally profitable as it looses the information about the AVL of the vector being inserted.  The result of this is that splats which could be done at a narrow VL, are instead done at VLMAX.  Given splats are generally scheduled close to their consuming instruction, this results in widespread regressions on RISCV if splat_vectors make it into dag combine.  (i.e. we end up needing to toggle VL repeatedly)

If desired, I could move the removed code into a target DAG for aarch64, but before doing that, I was hoping someone would have an idea on how to solve the generic problem in a profitable way.  :)  I don't know quite enough about AArch64 to know what's needed there, so pointers in the right direction are appreciated.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134061

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-insert-vector.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D134061.460838.patch
Type: text/x-patch
Size: 6915 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220916/1baeb833/attachment.bin>