[PATCH] D134024: [AArch64] Lower scalar sqxtn intrinsics to use fp registers

[Mingming Liu via Phabricator via llvm-commits]

mingmingl accepted this revision.
mingmingl added a comment.
This revision is now accepted and ready to land.

Thanks! LGTM (with a minor comment).



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4631
+      return DAG.getNode(ISD::BITCAST, SDLoc(Op), MVT::i32,
+                         DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(Op),
+                                     MVT::f32, Op.getOperand(0),
----------------
nit:

Use `dl` (created at line 4538), same for the other two `SDLoc(Op)`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134024/new/

https://reviews.llvm.org/D134024