[PATCH] D134032: [SROA] Check typeSizeEqualsStoreSize in isVectorPromotionViable

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope updated this revision to Diff 460750.
bjope added a comment.

Adding missing CHECKS to the new test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134032/new/

https://reviews.llvm.org/D134032

Files:
  llvm/lib/Transforms/Scalar/SROA.cpp
  llvm/test/Transforms/SROA/vector-promotion.ll


Index: llvm/test/Transforms/SROA/vector-promotion.ll
===================================================================
--- llvm/test/Transforms/SROA/vector-promotion.ll
+++ llvm/test/Transforms/SROA/vector-promotion.ll
@@ -628,3 +628,19 @@
   %add2 = add i32 %add, %add1
   ret i32 %add2
 }
+
+; This used to hit an assert after commit de3445e0ef15c4.
+; Added as regression test to verify that we handle this without crashing.
+define i1 @test15() {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT:    [[A_SROA_0:%.*]] = alloca <2 x i64>, align 32
+; CHECK-NEXT:    store <2 x i64> <i64 0, i64 -1>, ptr [[A_SROA_0]], align 32
+; CHECK-NEXT:    [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load i1, ptr [[A_SROA_0]], align 32
+; CHECK-NEXT:    ret i1 [[A_SROA_0_0_A_SROA_0_0_L]]
+;
+  %a = alloca <8 x i32>
+  store <2 x i64> <i64 0, i64 -1>, ptr %a
+  %l = load i1, ptr %a, align 1
+  ret i1 %l
+
+}
Index: llvm/lib/Transforms/Scalar/SROA.cpp
===================================================================
--- llvm/lib/Transforms/Scalar/SROA.cpp
+++ llvm/lib/Transforms/Scalar/SROA.cpp
@@ -1933,6 +1933,8 @@
       continue;
     if (isa<VectorType>(Ty))
       continue;
+    if (!DL.typeSizeEqualsStoreSize(Ty))
+      continue;
     // Create Vector with size of V, and each element of type Ty
     VectorType *V = CandidateTys[0];
     uint64_t ElementSize = DL.getTypeStoreSizeInBits(Ty).getFixedSize();


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