[PATCH] D127392: [AggressiveInstCombine] Combine consecutive loads which are being merged to form a wider load.
Biplob Mishra via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 16 06:00:28 PDT 2022
bipmis updated this revision to Diff 460709.
bipmis added a comment.
Update the patch with review comments.
-> Support power of 2 loads and minimum load size 8bits.
-> IR builder for new load.
-> New test for a 4 bit load.
-> Nits.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D127392/new/
https://reviews.llvm.org/D127392
Files:
llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
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