[PATCH] D133768: [DAGCombine] Do not fold SRA/SRL of MUL into MULH when MUL's LSB are used, and MUL_LOHI is available

[Juan Manuel Martinez Caamaño via Phabricator via llvm-commits]

jmmartinez updated this revision to Diff 460698.
jmmartinez added a comment.

- Use `!hasOneUse` instead of `use_size`
- renamed test from `mul_lohi.ll` to `dagcomb-mullohi.ll`
- named the instructions in the test using the `instnamer`
- generated test assertions using `update_llc_test_checks.py` (I wasn't familiar with it, I'm glad to know it now :) )
- added test-cases for
  - unsigned (already there)
  - signed
  - type for which mul_lohi is not legal
  - vector type
  - non-const shift
  - shift to the right by one more than the limit (so a v_mul_hi is used)
  - shift to the right by one less than the limit (so a v_mad is used)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133768/new/

https://reviews.llvm.org/D133768

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll

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