[PATCH] D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases

[Mingming Liu via Phabricator via llvm-commits]

mingmingl added a comment.

In D133850#3794139 <https://reviews.llvm.org/D133850#3794139>, @0x59616e wrote:

> In D133850#3789942 <https://reviews.llvm.org/D133850#3789942>, @mingmingl wrote:
>
>> Thanks for working on this! I got my hands tight on working on this [1] but I'm more than glad to collaborate on the review side as well!
>>
>> A high level question, https://reviews.llvm.org/D133280 has some other test cases for the same pattern, also on big-endian and little-endian systems to show the potential difference. It'd be great to generalize the current solution for those test cases. For simplicity, I'd probably start from solving the problem on little-endian first.
>>
>> Also, I found it helpful to keep these in mind while working on an implementation
>>
>> 1. the caveats of `BITCAST` (across vectors, or across vectors and scalars)
>> 2. memory layout of LLVM IR vectors
>>
>> https://reviews.llvm.org/D94964 answers the above two questions perfectly.
>>
>> [1] A preview of unfinished work in https://reviews.llvm.org/differential/diff/460138/ (not polished in terms of code style, and not generalized enough yet)
>
> Your implementation is more comprehensive than mine. Can I proceed the implementation with yours ?

Feel free to go ahead (we won't step on each others toes as long as only one of us is working on this and let the other people know). I think it could more general than the unfinished work (only optimizing two test cases).


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