[llvm] fdff1bb - [RISCV] Verify merge operand is tied properly

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-09-15T13:06:52-07:00
New Revision: fdff1bb10337fede736c6f8e858d93f2a8c86d1a

URL: https://github.com/llvm/llvm-project/commit/fdff1bb10337fede736c6f8e858d93f2a8c86d1a
DIFF: https://github.com/llvm/llvm-project/commit/fdff1bb10337fede736c6f8e858d93f2a8c86d1a.diff

LOG: [RISCV] Verify merge operand is tied properly

Differential Revision: https://reviews.llvm.org/D133957

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index ef7375195bf88..ba8af3867bbce 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -168,6 +168,12 @@ static inline bool usesMaskPolicy(uint64_t TSFlags) {
   return TSFlags & UsesMaskPolicyMask;
 }
 
+static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
+  assert(hasMergeOp(Desc.TSFlags));
+  assert(!Desc.isVariadic());
+  return Desc.getNumDefs();
+}
+
 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
   const uint64_t TSFlags = Desc.TSFlags;
   // This method is only called if we expect to have a VL operand, and all

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e205a8980b0c6..1afd2fb40f540 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1216,6 +1216,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
   }
 
   const uint64_t TSFlags = Desc.TSFlags;
+  if (RISCVII::hasMergeOp(TSFlags)) {
+    unsigned OpIdx = RISCVII::getMergeOpNum(Desc);
+    if (MI.findTiedOperandIdx(0) != OpIdx) {
+      ErrInfo = "Merge op improperly tied";
+      return false;
+    }
+  }
   if (RISCVII::hasVLOp(TSFlags)) {
     const MachineOperand &Op = MI.getOperand(RISCVII::getVLOpNum(Desc));
     if (!Op.isImm() && !Op.isReg())  {