[PATCH] D133953: [RISCV] Verify VL operand on instructions if present
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 15 09:35:35 PDT 2022
reames created this revision.
reames added reviewers: craig.topper, asb, frasercrmck, kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, hiraditya, arichardson, mcrosier.
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reames requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
These should only be immediate values or GPR registers.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D133953
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1220,6 +1220,21 @@
}
const uint64_t TSFlags = Desc.TSFlags;
+ if (RISCVII::hasVLOp(TSFlags)) {
+ const MachineOperand &Op = MI.getOperand(RISCVII::getVLOpNum(Desc));
+ if (!Op.isImm() && !Op.isReg()) {
+ ErrInfo = "Invalid operand type for VL operand";
+ return false;
+ }
+ if (Op.isReg() && Op.getReg() != RISCV::NoRegister) {
+ const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+ auto *RC = MRI.getRegClass(Op.getReg());
+ if (!RISCV::GPRRegClass.hasSubClassEq(RC)) {
+ ErrInfo = "Invalid register class for VL operand";
+ return false;
+ }
+ }
+ }
if (RISCVII::hasSEWOp(TSFlags)) {
unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
uint64_t Log2SEW = MI.getOperand(OpIdx).getImm();
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