[PATCH] D133495: [AArch64] Lower vector trunc using tbl.

[Florian Hahn via Phabricator via llvm-commits]

fhahn marked 2 inline comments as done.
fhahn added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13246-13247
+  Type *VecTy = FixedVectorType::get(Builder.getInt8Ty(), 16);
+  Parts.push_back(Builder.CreateBitCast(
+      Builder.CreateShuffleVector(TI->getOperand(0), {0, 1, 2, 3}), VecTy));
+  Parts.push_back(Builder.CreateBitCast(
----------------
t.p.northover wrote:
> Further to our big-endian discussion, I think this `bitcast` will put the least significant byte into elements 3, 7, 11, 15. So the for loop below should account for that.
Thanks, I adjusted the loop below to use Idx+3 for the mask to account for that on big-endian.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13324
     createTblShuffleForZExt(ZExt);
+    return true;
   }
----------------
t.p.northover wrote:
> Shouldn't this be part of the patch that adds the code above?
Yes, moved to D133494.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13327
+
+  // Convert 'trunc <(8|16) x i32> %x to <(8|16) x i32>' to a single tbl.4
+  // instruction selecting the lowest 8 bits per lane of the input interpreted
----------------
t.p.northover wrote:
> Destination type wrong.
Thanks, should be fixed!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133495/new/

https://reviews.llvm.org/D133495