[PATCH] D131865: Pre-commit test for D131587

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=7 -o - %s | FileCheck %s
 
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Why do you need to increase this? This just forces you to make the test functions bigger? If it's just for the new test, I'd rather split that into a separate file


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Comment at: llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll:3413-3422
+; CHECK-NEXT:    s_mov_b32 vcc_hi, vcc_lo
+; CHECK-NEXT:    s_mov_b32 vcc_lo, s101
+; CHECK-NEXT:    s_mov_b32 s101, s100
+; CHECK-NEXT:    s_mov_b32 s100, s99
+; CHECK-NEXT:    s_mov_b32 s99, s98
+; CHECK-NEXT:    s_mov_b32 s98, s97
+; CHECK-NEXT:    s_mov_b32 s97, s96
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piggynl wrote:
> and I don't know why this sequence is forming. Is this intended?
Do you mean the copies to shift down by one? I'd guess this is somehow related to the asm sequence trying to use a bunch of reserved registers as if they were all allocatable, and with such high register usage you hit some poor allocation decision


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  https://reviews.llvm.org/D131865/new/

https://reviews.llvm.org/D131865