[llvm] bea33f7 - [M68k] Fix the crash of fast register allocator
via llvm-commits
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Wed Sep 14 18:24:43 PDT 2022
Author: Sheng
Date: 2022-09-15T09:24:22+08:00
New Revision: bea33f75e2bf1cbe3fd61b3ff7d2cc0b99391588
URL: https://github.com/llvm/llvm-project/commit/bea33f75e2bf1cbe3fd61b3ff7d2cc0b99391588
DIFF: https://github.com/llvm/llvm-project/commit/bea33f75e2bf1cbe3fd61b3ff7d2cc0b99391588.diff
LOG: [M68k] Fix the crash of fast register allocator
`MOVEM` is used to spill the register, which will cause problem with 1 byte data, since it only supports word (2 bytes) and long (4 bytes) size.
We change to use the normal `move` instruction to spill 1 byte data.
Fixes #57660
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D133636
Added:
llvm/test/CodeGen/M68k/PR57660.ll
Modified:
llvm/lib/Target/M68k/M68kInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 563f80967ed47..ca64dc191e5ca 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -702,7 +702,7 @@ unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC,
llvm_unreachable("Unknown spill size");
case 8:
if (M68k::DR8RegClass.hasSubClassEq(RC))
- return load ? M68k::MOVM8mp_P : M68k::MOVM8pm_P;
+ return load ? M68k::MOV8dp : M68k::MOV8pd;
if (M68k::CCRCRegClass.hasSubClassEq(RC))
return load ? M68k::MOV16cp : M68k::MOV16pc;
@@ -745,9 +745,10 @@ void M68kInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- const MachineFunction &MF = *MBB.getParent();
- assert(MF.getFrameInfo().getObjectSize(FrameIndex) == 4 &&
- "Stack slot too small for store");
+ const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
+ assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) &&
+ "Stack slot is too small to store");
+
unsigned Opc = getStoreRegOpcode(SrcReg, RC, TRI, Subtarget);
DebugLoc DL = MBB.findDebugLoc(MI);
// (0,FrameIndex) <- $reg
@@ -760,9 +761,10 @@ void M68kInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Register DstReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- const MachineFunction &MF = *MBB.getParent();
- assert(MF.getFrameInfo().getObjectSize(FrameIndex) == 4 &&
- "Stack slot too small for load");
+ const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
+ assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) &&
+ "Stack slot is too small to load");
+
unsigned Opc = getLoadRegOpcode(DstReg, RC, TRI, Subtarget);
DebugLoc DL = MBB.findDebugLoc(MI);
M68k::addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DstReg), FrameIndex);
diff --git a/llvm/test/CodeGen/M68k/PR57660.ll b/llvm/test/CodeGen/M68k/PR57660.ll
new file mode 100644
index 0000000000000..31fa61658fcb0
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/PR57660.ll
@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k-linux-gnu --regalloc=fast %s -o - | FileCheck %s
+
+define dso_local void @foo1() {
+; CHECK-LABEL: foo1:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %entry
+; CHECK-NEXT: suba.l #2, %sp
+; CHECK-NEXT: .cfi_def_cfa_offset -6
+; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: .LBB0_1: ; %do.body
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT: cmpi.b #0, %d0
+; CHECK-NEXT: bne .LBB0_1
+; CHECK-NEXT: ; %bb.2: ; %do.end
+; CHECK-NEXT: adda.l #2, %sp
+; CHECK-NEXT: rts
+entry:
+ br label %do.body
+
+do.body: ; preds = %land.end, %entry
+ %cmp5 = icmp eq i32 0, 4
+ br label %land.end
+
+land.end: ; preds = %do.body
+ br i1 %cmp5, label %do.body, label %do.end
+
+do.end: ; preds = %land.end
+ ret void
+}
+
+define i32 @foo2(ptr noundef %0) {
+; CHECK-LABEL: foo2:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %entry
+; CHECK-NEXT: suba.l #4, %sp
+; CHECK-NEXT: .cfi_def_cfa_offset -8
+; CHECK-NEXT: move.l (8,%sp), %a0
+; CHECK-NEXT: move.b (%a0), %d0
+; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: and.b #1, %d0
+; CHECK-NEXT: move.b %d0, (2,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: sub.b #1, %d0
+; CHECK-NEXT: bgt .LBB1_2
+; CHECK-NEXT: ; %bb.1: ; %if
+; CHECK-NEXT: move.b (2,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT: move.b (0,%sp), %d1 ; 1-byte Folded Reload
+; CHECK-NEXT: add.b %d1, %d0
+; CHECK-NEXT: bra .LBB1_3
+; CHECK-NEXT: .LBB1_2: ; %else
+; CHECK-NEXT: move.b (2,%sp), %d1 ; 1-byte Folded Reload
+; CHECK-NEXT: move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT: sub.b %d1, %d0
+; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: .LBB1_3: ; %cont
+; CHECK-NEXT: move.b %d0, (2,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: move.b (2,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT: ext.w %d0
+; CHECK-NEXT: ext.l %d0
+; CHECK-NEXT: adda.l #4, %sp
+; CHECK-NEXT: rts
+entry:
+ %1 = getelementptr i8, ptr %0, i32 0
+ %2 = load i8, ptr %1
+ %3 = and i8 %2, 1
+ %4 = icmp sle i8 %3, 1
+ br i1 %4, label %if, label %else
+
+if:
+ %5 = add i8 %3, %2
+ br label %cont
+
+else:
+ %6 = sub i8 %2, %3
+ br label %cont
+
+cont:
+ %7 = phi i8 [%5, %if], [%6, %else]
+ %8 = sext i8 %7 to i32
+ ret i32 %8
+}
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