[PATCH] D133905: [RISCV] Simplify some code in RISCVInstrInfo::verifyInstruction. NFCI
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 14 16:00:24 PDT 2022
craig.topper created this revision.
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This code was written as if it lived in the MC layer instead of
the CodeGen layer. We get the MCInstrDesc directly from MachineInstr.
And we can use RISCVSubtarget::is64Bit instead of going to the
Triple.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D133905
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1127,8 +1127,7 @@
bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const {
- const MCInstrInfo *MCII = STI.getInstrInfo();
- MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
+ MCInstrDesc const &Desc = MI.getDesc();
for (auto &OI : enumerate(Desc.operands())) {
unsigned OpType = OI.value().OperandType;
@@ -1195,17 +1194,14 @@
Ok = isShiftedInt<7, 5>(Imm);
break;
case RISCVOp::OPERAND_UIMMLOG2XLEN:
- Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
- : isUInt<5>(Imm);
+ Ok = STI.is64Bit() ? isUInt<6>(Imm) : isUInt<5>(Imm);
break;
case RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO:
- Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
- : isUInt<5>(Imm);
+ Ok = STI.is64Bit() ? isUInt<6>(Imm) : isUInt<5>(Imm);
Ok = Ok && Imm != 0;
break;
case RISCVOp::OPERAND_UIMM_SHFL:
- Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<5>(Imm)
- : isUInt<4>(Imm);
+ Ok = STI.is64Bit() ? isUInt<5>(Imm) : isUInt<4>(Imm);
break;
case RISCVOp::OPERAND_RVKRNUM:
Ok = Imm >= 0 && Imm <= 10;
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