[PATCH] D133869: [RISCV] Verify SEW/VecPolicy immediate values
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 14 13:14:19 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1226
+ unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
+ unsigned Log2SEW = MI.getOperand(OpIdx).getImm();
+ unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
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The immediate operand stores 64 bits, should we check all 64 bits and make sure its small enough to be a shift amount before using it to shift?
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1235
+ unsigned OpIdx = RISCVII::getVecPolicyOpNum(Desc);
+ unsigned Policy = MI.getOperand(OpIdx).getImm();
+ if (Policy > (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) {
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Should we check all 64 bits of the immediate?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D133869/new/
https://reviews.llvm.org/D133869
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