[llvm] 3acaf04 - [LLVM][AArch64] Don't warn about clobbering X16 when Speculative Load Hardening is used

[David Spickett via llvm-commits]

Author: David Spickett
Date: 2022-09-14T15:19:53Z
New Revision: 3acaf04033a5128ea6e5dbfee9827e2af709b013

URL: https://github.com/llvm/llvm-project/commit/3acaf04033a5128ea6e5dbfee9827e2af709b013
DIFF: https://github.com/llvm/llvm-project/commit/3acaf04033a5128ea6e5dbfee9827e2af709b013.diff

LOG: [LLVM][AArch64] Don't warn about clobbering X16 when Speculative Load Hardening is used

SLH will fall back to a different technique if X16 is being used,
so there is no need to warn for inline asm use. Only prevent other codegen
from using it.

Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D133766

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 164471f2a917a..f92fccac21dbb 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -421,6 +421,13 @@ void AArch64RegisterInfo::emitReservedArgRegCallError(
 
 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                           MCRegister PhysReg) const {
+  // SLH uses register X16 as the taint register but it will fallback to a 
diff erent
+  // method if the user clobbers it. So X16 is not reserved for inline asm but is
+  // for normal codegen.
+  if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) &&
+        MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
+    return true;
+
   return !isReservedReg(MF, PhysReg);
 }
 

diff  --git a/llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll b/llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll
index 0f16235d7c69e..503417bc51d67 100644
--- a/llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll
+++ b/llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll
@@ -1,5 +1,10 @@
-; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,SLH
-; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,NOSLH
+; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu 2>&1 | FileCheck %s --check-prefixes=CHECK,SLH
+; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu 2>&1 | FileCheck %s --check-prefixes=CHECK,NOSLH
+
+; As SLH is falling back to a technique that doesn't use X16, we shouldn't see any warnings about clobbers.
+; (this would come from f_clobbered_reg_w16, but warnings are first in the output)
+; CHECK-NOT: warning: inline asm clobber list contains reserved registers: W16
+; CHECK-NOT: warning: inline asm clobber list contains reserved registers: X16
 
 declare i64 @g(i64, i64) local_unnamed_addr
 define i64 @f_using_reserved_reg_x16(i64 %a, i64 %b) local_unnamed_addr SLHATTR {