[PATCH] D133766: [LLVM][AArch64] Explain why X16 is reserved when Speculative Load Hardening is in use

[David Spickett via Phabricator via llvm-commits]

DavidSpickett updated this revision to Diff 459757.
DavidSpickett added a comment.

Instead, don't warn for inline asm clobber of x16 at all.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133766/new/

https://reviews.llvm.org/D133766

Files:
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll


Index: llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll
===================================================================
--- llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll
+++ llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll
@@ -1,5 +1,10 @@
-; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,SLH
-; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,NOSLH
+; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu 2>&1 | FileCheck %s --check-prefixes=CHECK,SLH
+; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu 2>&1 | FileCheck %s --check-prefixes=CHECK,NOSLH
+
+; As SLH is falling back to a technique that doesn't use X16, we shouldn't see any warnings about clobbers.
+; (this would come from f_clobbered_reg_w16, but warnings are first in the output)
+; CHECK-NOT: warning: inline asm clobber list contains reserved registers: W16
+; CHECK-NOT: warning: inline asm clobber list contains reserved registers: X16
 
 declare i64 @g(i64, i64) local_unnamed_addr
 define i64 @f_using_reserved_reg_x16(i64 %a, i64 %b) local_unnamed_addr SLHATTR {
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -421,6 +421,13 @@
 
 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                           MCRegister PhysReg) const {
+  // SLH uses register X16 as the taint register but it will fallback to a different
+  // method if the user clobbers it. So X16 is not reserved for inline asm but is
+  // for normal codegen.
+  if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) &&
+        MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
+    return true;
+
   return !isReservedReg(MF, PhysReg);
 }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D133766.459757.patch
Type: text/x-patch
Size: 2155 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220913/9a7de8f1/attachment.bin>