[PATCH] D133766: [LLVM][AArch64] Explain why X16 is reserved when Speculative Load Hardening is in use

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls added a comment.

I seem to remember that the speculative_load_hardening for AArch64 has a work-around when a user does reserve register X16 in inline assembly, see comment at https://github.com/llvm/llvm-project/blob/b7dae832e61da1f8b48cce1715514cbd5809eb3f/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp#L35.
Given that comment and the tests in https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll that check that behaviour, the warning/error implemented in this patch is not correct?



================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp:342
+    return std::string(
+        "X16 is used as the taint register for Speculative Load Hardening.");
+
----------------
I see that I've used the term "taint register" in the source code of AArch64SpeculationHardening.cpp; but I don't see the term in the (X86-centric) design document about Speculative Load Hardening at https://llvm.org/docs/SpeculativeLoadHardening.html. I don't immediately see an alternative term to clearly name the register that Speculative Load Hardening reserves.
Therefore, I think that using the term "taint register" is indeed the best option available here.


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