[PATCH] D133723: [AMDGPU][GFX11] Use VGPR_32_F128 for VOP1,2,C

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp:144
 
+/// Only shrink 16 bit registers after RA.
+/// Do not shrink the instruction if its registers are not expressible in the
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I would prefer to change SIShrinkInstructions in a more general way that does not specifically check for True16 instructions: D133769


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133723/new/

https://reviews.llvm.org/D133723