[PATCH] D133769: [AMDGPU] Don't shrink VOP3 instructions pre-RA on GFX10+

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added a reviewer: AMDGPU.
Herald added subscribers: kosarev, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm, MatzeB.
Herald added a project: All.
foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

In GFX10, there is no advantage to shrinking these instructions pre-RA,
so this just saves a bit of work.

In GFX11 there is an advantage to *not* shrinking them pre-RA, because
the register classes for 16-bit operands are less restrictive in the
VOP3 form than in the shrunk form. This patch is a prerequisite for
actually setting up those register classes correctly for 16-bit vs
non-16-bit operands.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133769

Files:
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir
  llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
  llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D133769.459720.patch
Type: text/x-patch
Size: 54328 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220913/85619624/attachment.bin>