[PATCH] D133766: [LLVM][AArch64] Explain why X16 is reserved when Speculative Load Hardening is in use

[David Spickett via Phabricator via llvm-commits]

DavidSpickett updated this revision to Diff 459707.
DavidSpickett added a comment.

newline at end of test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133766/new/

https://reviews.llvm.org/D133766

Files:
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/test/CodeGen/AArch64/inline-asm-clobber-slh-taint.ll


Index: llvm/test/CodeGen/AArch64/inline-asm-clobber-slh-taint.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/inline-asm-clobber-slh-taint.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu %s 2>&1 | FileCheck %s
+
+; CHECK: warning: inline asm clobber list contains reserved registers: X16
+; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+; CHECK-NEXT: note: X16 is used as the taint register for Speculative Load Hardening.
+
+define void @fx() speculative_load_hardening {
+entry:
+  call void asm sideeffect "nop", "~{x16}"()
+  ret void
+}
+
+; CHECK: warning: inline asm clobber list contains reserved registers: W16
+; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+; CHECK-NEXT: note: X16 is used as the taint register for Speculative Load Hardening.
+
+define void @fw() speculative_load_hardening {
+entry:
+  call void asm sideeffect "nop", "~{w16}"()
+  ret void
+}
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -312,6 +312,8 @@
 llvm::Optional<std::string>
 AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
                                         MCRegister PhysReg) const {
+  // In cases like this where the clobber might be a W register, the message
+  // always uses the X name because the purpose it is reserved for uses the full 64 bits.
   if (hasBasePointer(MF) && MCRegisterInfo::regsOverlap(PhysReg, AArch64::X19))
     return std::string("X19 is used as the frame base pointer register.");
 
@@ -333,6 +335,10 @@
              " is clobbered by asynchronous signals when using Arm64EC.";
   }
 
+  if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) &&
+        MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
+    return std::string("X16 is used as the taint register for Speculative Load Hardening.");
+
   return {};
 }
 


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