[PATCH] D133723: [AMDGPU][GFX11] Use VGPR_32_F128 for VOP1,2,C

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

> We introduce a new register class VGPR_32_F128 which is used for
> encodings VOP1, VOP2, and VOPC. This register class only has the first
> 128 VGPRs, but is otherwise identical to VGPR_32. Therefore, VOP1, VOP2,
> and VOPC instructions are correctly limited to use the first 128
> VGPRs, while the other instructions can freely use all 256.

This paragraph needs to explain that the new register class is used for 16-bit operands only. The whole point of this patch is that 32-bit operands will no longer be restricted to using the first 128 VGPRs.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D133723/new/

https://reviews.llvm.org/D133723