[PATCH] D133723: [AMDGPU][GFX11] Use VGPR_32_F128 for VOP1,2,C

[Joe Nash via Phabricator via llvm-commits]

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Due to the encoding changes in GFX11, we had a hack in place that
disables the use of VGPRs above 128. This patch removes the need for
that hack.

We introduce a new register class VGPR_32_F128 which is used for
encodings VOP1, VOP2, and VOPC. This register class only has the first
128 VGPRs, but is otherwise identical to VGPR_32. Therefore, VOP1, VOP2,
and VOPC instructions are correctly limited to use the first 128
VGPRs, while the other instructions can freely use all 256.

We introduce new pseduo-instructions used on GFX11 which have the suffix
T16 (True16) to use the VGPR_32_F128 register class.

We do not shrink _e64 instructions to _e32 encodings
(typically VOP1, VOP2, VOPC) before register allocation to prioritize good
allocations above code size.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133723

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  llvm/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/lib/Target/AMDGPU/VOPCInstructions.td
  llvm/lib/Target/AMDGPU/VOPInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
  llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
  llvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir
  llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
  llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
  llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
  llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
  llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
  llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
  llvm/test/CodeGen/AMDGPU/true16-ra-f128-fail.mir
  llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
  llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
  llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
  llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
  llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
  llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
  llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
  llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
  llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
  llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
  llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s

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