[PATCH] D133673: [NFC][msan] Convert some code to early returns

Vitaly Buka via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 12 12:54:20 PDT 2022


vitalybuka marked 2 inline comments as done.
vitalybuka added inline comments.


================
Comment at: llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp:3274
 
+    Value *ShadowPtr;
+    Value *OriginPtr;
----------------
fmayer wrote:
> Why is this reordering necessary? For consistency with below?
for readability
I think original code is harder to follow


================
Comment at: llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll:100
 ; ADDR-NEXT:  entry:
-; ADDR-NEXT:    [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8
-; ADDR-NEXT:    [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8
-; ADDR-NEXT:    [[TMP2:%.*]] = load <4 x i1>, <4 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i1>*), align 8
+; ADDR-NEXT:    [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8
+; ADDR-NEXT:    [[TMP1:%.*]] = load <4 x i1>, <4 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i1>*), align 8
----------------
fmayer wrote:
> is this still considered [NFC] if it changes IR?
yes, if IR change is NFC :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133673/new/

https://reviews.llvm.org/D133673



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