[llvm] 4186a49 - [RISCV] Custom type legalize i32 loads by sign extending.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 12 09:13:47 PDT 2022
Author: Craig Topper
Date: 2022-09-12T09:13:07-07:00
New Revision: 4186a49d793eb69afee7a724dad87a8ecd434e51
URL: https://github.com/llvm/llvm-project/commit/4186a49d793eb69afee7a724dad87a8ecd434e51
DIFF: https://github.com/llvm/llvm-project/commit/4186a49d793eb69afee7a724dad87a8ecd434e51.diff
LOG: [RISCV] Custom type legalize i32 loads by sign extending.
The default is to use extload which can become a zextload or
sextload if it is followed by an 'and' or sext_inreg.
Sometimes type legalization will introduce an 'and' from promoting
something like 'srl X, C' and a sext_inreg from from a setcc. The
'and' could be freely folded with the promoted 'srl' by using srliw,
but the sext_inreg can't be folded into a compare. DAG combiner
will see both of these choices and may decide to fold the 'and'
instead of the 'sext_inreg'. This forces the sext_inreg to become
a sext.w.
By picking sextload in the type legalizer we take this choice away.
Looking at spec2006 compiled with Zba and Zbb this appeared to be
net reduction in lines of code in the objdump disassembly output.
This is similar to what we do with i32 add/sub/mul/shl in
type legalization where we always emit a sext_inreg.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D130397
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/sextw-removal.ll
llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8fd3570e52949..e621c3455050a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -179,6 +179,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, XLenVT,
MVT::i1, Promote);
+ // DAGCombiner can call isLoadExtLegal for types that aren't legal.
+ setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i32,
+ MVT::i1, Promote);
// TODO: add all necessary setOperationAction calls.
setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand);
@@ -210,6 +213,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.is64Bit()) {
setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
+ setOperationAction(ISD::LOAD, MVT::i32, Custom);
+
setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
MVT::i32, Custom);
@@ -7087,6 +7092,22 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(RCW.getValue(2));
break;
}
+ case ISD::LOAD: {
+ if (!ISD::isNON_EXTLoad(N))
+ return;
+
+ // Use a SEXTLOAD instead of the default EXTLOAD. Similar to the
+ // sext_inreg we emit for ADD/SUB/MUL/SLLI.
+ LoadSDNode *Ld = cast<LoadSDNode>(N);
+
+ SDLoc dl(N);
+ SDValue Res = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Ld->getChain(),
+ Ld->getBasePtr(), Ld->getMemoryVT(),
+ Ld->getMemOperand());
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Res));
+ Results.push_back(Res.getValue(1));
+ return;
+ }
case ISD::MUL: {
unsigned Size = N->getSimpleValueType(0).getSizeInBits();
unsigned XLen = Subtarget.getXLen();
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index 7b382d30dcd64..0e3a33c5ae66d 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -65,9 +65,10 @@ bb7: ; preds = %bb2
declare signext i32 @bar(i32 signext)
-; The load here will be an anyext load in isel and sext.w will be emitted for
-; the ret. Make sure we can look through logic ops to prove the sext.w is
-; unnecessary.
+; The load here was previously an aext load, but this has since been changed
+; to a signext load allowing us to remove a sext.w before isel. Thus we get
+; the same result with or without the sext.w removal pass.
+; Test has been left for coverage purposes.
define signext i32 @test2(i32* %p, i32 signext %b) nounwind {
; RV64I-LABEL: test2:
; RV64I: # %bb.0:
@@ -92,7 +93,6 @@ define signext i32 @test2(i32* %p, i32 signext %b) nounwind {
; NOREMOVAL-NEXT: li a2, -2
; NOREMOVAL-NEXT: rolw a1, a2, a1
; NOREMOVAL-NEXT: and a0, a1, a0
-; NOREMOVAL-NEXT: sext.w a0, a0
; NOREMOVAL-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
@@ -125,7 +125,6 @@ define signext i32 @test3(i32* %p, i32 signext %b) nounwind {
; NOREMOVAL-NEXT: li a2, -2
; NOREMOVAL-NEXT: rolw a1, a2, a1
; NOREMOVAL-NEXT: or a0, a1, a0
-; NOREMOVAL-NEXT: sext.w a0, a0
; NOREMOVAL-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
@@ -158,7 +157,6 @@ define signext i32 @test4(i32* %p, i32 signext %b) nounwind {
; NOREMOVAL-NEXT: li a2, 1
; NOREMOVAL-NEXT: sllw a1, a2, a1
; NOREMOVAL-NEXT: xnor a0, a1, a0
-; NOREMOVAL-NEXT: sext.w a0, a0
; NOREMOVAL-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
diff --git a/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll b/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
index 0139d8009a2e9..794f8d39003a5 100644
--- a/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
+++ b/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
@@ -46,7 +46,7 @@ define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
;
; RV64-LABEL: vec3_setcc_crash:
; RV64: # %bb.0:
-; RV64-NEXT: lwu a0, 0(a0)
+; RV64-NEXT: lw a0, 0(a0)
; RV64-NEXT: slli a2, a0, 40
; RV64-NEXT: slli a3, a0, 56
; RV64-NEXT: slli a4, a0, 48
@@ -73,7 +73,7 @@ define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
; RV64-NEXT: li a0, 0
; RV64-NEXT: j .LBB0_8
; RV64-NEXT: .LBB0_7:
-; RV64-NEXT: srli a0, a0, 16
+; RV64-NEXT: srliw a0, a0, 16
; RV64-NEXT: .LBB0_8:
; RV64-NEXT: sb a0, 2(a1)
; RV64-NEXT: sh a2, 0(a1)
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