[llvm] f912d0d - [AMDGPU] Change test check name. NFC

Joe Nash via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 12 07:09:08 PDT 2022 

Author: Joe Nash
Date: 2022-09-12T09:28:55-04:00
New Revision: f912d0d6e17be4338bd0bb9ee519f62b4cc74579

URL: https://github.com/llvm/llvm-project/commit/f912d0d6e17be4338bd0bb9ee519f62b4cc74579
DIFF: https://github.com/llvm/llvm-project/commit/f912d0d6e17be4338bd0bb9ee519f62b4cc74579.diff

LOG: [AMDGPU] Change test check name. NFC

Change the check name from GFX10 to GFX10Plus to refect its actual usage

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/preserve-hi16.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll b/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
index 0adcc5427282..1fdd1b40def6 100644
--- a/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
+++ b/llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX900 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX906 %s
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10Plus %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10Plus %s
 
 ; GCN-LABEL: {{^}}shl_i16:
 ; GCN: v_lshlrev_b16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
@@ -90,7 +90,7 @@ define i16 @max_i16(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}shl_i16_zext_i32:
 ; GCN: v_lshlrev_b16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @shl_i16_zext_i32(i16 %x, i16 %y) {
   %res = shl i16 %x, %y
@@ -100,7 +100,7 @@ define i32 @shl_i16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}lshr_i16_zext_i32:
 ; GCN: v_lshrrev_b16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @lshr_i16_zext_i32(i16 %x, i16 %y) {
   %res = lshr i16 %x, %y
@@ -110,7 +110,7 @@ define i32 @lshr_i16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}ashr_i16_zext_i32:
 ; GCN: v_ashrrev_i16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @ashr_i16_zext_i32(i16 %x, i16 %y) {
   %res = ashr i16 %x, %y
@@ -120,7 +120,7 @@ define i32 @ashr_i16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}add_u16_zext_i32:
 ; GCN: v_add_{{(nc_)*}}u16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @add_u16_zext_i32(i16 %x, i16 %y) {
   %res = add i16 %x, %y
@@ -130,7 +130,7 @@ define i32 @add_u16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}sub_u16_zext_i32:
 ; GCN: v_sub_{{(nc_)*}}u16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @sub_u16_zext_i32(i16 %x, i16 %y) {
   %res = sub i16 %x, %y
@@ -140,7 +140,7 @@ define i32 @sub_u16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}mul_lo_u16_zext_i32:
 ; GCN: v_mul_lo_u16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @mul_lo_u16_zext_i32(i16 %x, i16 %y) {
   %res = mul i16 %x, %y
@@ -150,7 +150,7 @@ define i32 @mul_lo_u16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}min_u16_zext_i32:
 ; GCN: v_min_u16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @min_u16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp ule i16 %x, %y
@@ -161,7 +161,7 @@ define i32 @min_u16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}min_i16_zext_i32:
 ; GCN: v_min_i16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @min_i16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp sle i16 %x, %y
@@ -172,7 +172,7 @@ define i32 @min_i16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}max_u16_zext_i32:
 ; GCN: v_max_u16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @max_u16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp uge i16 %x, %y
@@ -183,7 +183,7 @@ define i32 @max_u16_zext_i32(i16 %x, i16 %y) {
 
 ; GCN-LABEL: {{^}}max_i16_zext_i32:
 ; GCN: v_max_i16{{(_e32|_e64)?}} [[OP:v[0-9]+]],
-; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
+; GFX10Plus-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @max_i16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp sge i16 %x, %y
@@ -199,8 +199,8 @@ define i32 @max_i16_zext_i32(i16 %x, i16 %y) {
 ; GFX9: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1
 ; GFX9-NEXT: s_setpc_b64
 
-; GFX10: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, [[ADD]]
+; GFX10Plus: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1
+; GFX10Plus-NEXT: v_and_b32_e32 v0, 0xffff, [[ADD]]
 define i32 @zext_fadd_f16(half %x, half %y) {
   %add = fadd half %x, %y
   %cast = bitcast half %add to i16
@@ -215,8 +215,8 @@ define i32 @zext_fadd_f16(half %x, half %y) {
 ; GFX9: v_fma_f16 [[FMA:v[0-9]+]], v0, v1, v2
 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, [[FMA]]
 
-; GFX10: v_fmac_f16_e32 [[FMA:v[0-9]+]], v0, v1
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, [[FMA]]
+; GFX10Plus: v_fmac_f16_e32 [[FMA:v[0-9]+]], v0, v1
+; GFX10Plus-NEXT: v_and_b32_e32 v0, 0xffff, [[FMA]]
 define i32 @zext_fma_f16(half %x, half %y, half %z) {
   %fma = call half @llvm.fma.f16(half %x, half %y, half %z)
   %cast = bitcast half %fma to i16
@@ -231,8 +231,8 @@ define i32 @zext_fma_f16(half %x, half %y, half %z) {
 ; GFX9: v_div_fixup_f16 v0, v0, v1, v2
 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
 
-; GFX10: v_div_fixup_f16 v0, v0, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10Plus: v_div_fixup_f16 v0, v0, v1, v2
+; GFX10Plus-NEXT: v_and_b32_e32 v0, 0xffff, v0
 define i32 @zext_div_fixup_f16(half %x, half %y, half %z) {
   %div.fixup = call half @llvm.amdgcn.div.fixup.f16(half %x, half %y, half %z)
   %cast = bitcast half %div.fixup to i16
@@ -251,8 +251,8 @@ define i32 @zext_div_fixup_f16(half %x, half %y, half %z) {
 ; GFX9: v_cvt_f16_f32_e32 v0, v0
 ; GFX9-NEXT: s_setpc_b64
 
-; GFX10: v_cvt_f16_f32_e32 v0, v0
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10Plus: v_cvt_f16_f32_e32 v0, v0
+; GFX10Plus-NEXT: v_and_b32_e32 v0, 0xffff, v0
 define i32 @zext_fptrunc_f16(float %x) {
   %fptrunc = fptrunc float %x to half
   %cast = bitcast half %fptrunc to i16
@@ -272,8 +272,8 @@ define i32 @zext_fptrunc_f16(float %x) {
 ; GFX906: v_fma_mixlo_f16 v0, v0, v1, v2
 ; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
 
-; GFX10: v_fma_mixlo_f16 v0, v0, v1, v2
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10Plus: v_fma_mixlo_f16 v0, v0, v1, v2
+; GFX10Plus-NEXT: v_and_b32_e32 v0, 0xffff, v0
 define i32 @zext_fptrunc_fma_f16(float %x, float %y, float %z) {
   %fma = call float @llvm.fma.f32(float %x, float %y, float %z)
   %fptrunc = fptrunc float %fma to half

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