[PATCH] D133421: [AArch64] break non-temporal loads over 256 into 256-loads and a smaller load

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17860
+      DAG.getMemBasePlusOffset(BasePtr, TypeSize::Fixed(PtrOffset), DL, Flags);
+  Align NewAlign = commonAlignment(LD->getAlign(), MemVT.getSizeInBits());
+  SDValue RemainingLoad =
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t.p.northover wrote:
> Shouldn't the second operand of this call be `PtrOffset` again?
Yes it should be, it is worth noting that the offsets on the generated assembly didn't change when I changed from using `MemVT.getSizeInBits())` to `PtrOffset`


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  https://reviews.llvm.org/D133421/new/

https://reviews.llvm.org/D133421