[PATCH] D133584: [DAGCombiner] [AMDGPU] Allow vector loads in MatchLoadCombine

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7955
+
+    int VectorIndex = static_cast<int>(OffsetOp->getZExtValue());
+    assert(static_cast<uint64_t>(VectorIndex) == OffsetOp->getZExtValue());
----------------
Why implicitly cast to int to assert the value? Just use uint64_t?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7963
+    bool breaksPattern =
+        static_cast<uint64_t>(StartingIndex) != OffsetOp->getZExtValue();
+
----------------
Early return on condition instead of wrapping ternary operator


================
Comment at: llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
----------------
Don’t need -O3?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D133584/new/

https://reviews.llvm.org/D133584