[llvm] 8901f7c - [AMDGPU] Fix crash legalizing G_EXTRACT_VECTOR_ELT with negative index

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2022-09-09T15:53:34+01:00
New Revision: 8901f7cebc73383d0cda19a870ffe410a67653e9

URL: https://github.com/llvm/llvm-project/commit/8901f7cebc73383d0cda19a870ffe410a67653e9
DIFF: https://github.com/llvm/llvm-project/commit/8901f7cebc73383d0cda19a870ffe410a67653e9.diff

LOG: [AMDGPU] Fix crash legalizing G_EXTRACT_VECTOR_ELT with negative index

Fixes https://github.com/llvm/llvm-project/issues/57408

Differential Revision: https://reviews.llvm.org/D132938

Added: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 0979debe9777d..58ab8720638d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2343,7 +2343,7 @@ bool AMDGPULegalizerInfo::legalizeExtractVectorElt(
       getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI);
   if (!MaybeIdxVal) // Dynamic case will be selected to register indexing.
     return true;
-  const int64_t IdxVal = MaybeIdxVal->Value.getSExtValue();
+  const uint64_t IdxVal = MaybeIdxVal->Value.getZExtValue();
 
   Register Dst = MI.getOperand(0).getReg();
   Register Vec = MI.getOperand(1).getReg();
@@ -2378,7 +2378,7 @@ bool AMDGPULegalizerInfo::legalizeInsertVectorElt(
   if (!MaybeIdxVal) // Dynamic case will be selected to register indexing.
     return true;
 
-  int64_t IdxVal = MaybeIdxVal->Value.getSExtValue();
+  const uint64_t IdxVal = MaybeIdxVal->Value.getZExtValue();
   Register Dst = MI.getOperand(0).getReg();
   Register Vec = MI.getOperand(1).getReg();
   Register Ins = MI.getOperand(2).getReg();

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
new file mode 100644
index 0000000000000..b5dca793bc507
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: f
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: f
+    ; CHECK: SI_RETURN
+    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+
+    %2:_(s32) = G_CONSTANT i32 -1
+    %3:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %2(s32)
+    %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %3(s32), %2(s32)
+
+    %5:_(s32) = G_CONSTANT i32 2
+    %6:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %5(s32)
+    %7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %6(s32), %5(s32)
+
+    %8:_(s1) = G_CONSTANT i1 1
+    %9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s1)
+    %10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %8(s1)
+
+    SI_RETURN
+...