[PATCH] D132938: [AMDGPU] Fix crash legalizing G_EXTRACT_VECTOR_ELT with negative index

[Jay Foad via Phabricator via llvm-commits]

foad updated this revision to Diff 458996.
foad added a comment.

Switch to MIR test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132938/new/

https://reviews.llvm.org/D132938

Files:
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir


Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: f
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: f
+    ; CHECK: SI_RETURN
+    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+
+    %2:_(s32) = G_CONSTANT i32 -1
+    %3:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %2(s32)
+    %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %3(s32), %2(s32)
+
+    %5:_(s32) = G_CONSTANT i32 2
+    %6:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %5(s32)
+    %7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %6(s32), %5(s32)
+
+    %8:_(s1) = G_CONSTANT i1 1
+    %9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s1)
+    %10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %8(s1)
+
+    SI_RETURN
+...
Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2343,7 +2343,7 @@
       getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI);
   if (!MaybeIdxVal) // Dynamic case will be selected to register indexing.
     return true;
-  const int64_t IdxVal = MaybeIdxVal->Value.getSExtValue();
+  const uint64_t IdxVal = MaybeIdxVal->Value.getZExtValue();
 
   Register Dst = MI.getOperand(0).getReg();
   Register Vec = MI.getOperand(1).getReg();
@@ -2378,7 +2378,7 @@
   if (!MaybeIdxVal) // Dynamic case will be selected to register indexing.
     return true;
 
-  int64_t IdxVal = MaybeIdxVal->Value.getSExtValue();
+  const uint64_t IdxVal = MaybeIdxVal->Value.getZExtValue();
   Register Dst = MI.getOperand(0).getReg();
   Register Vec = MI.getOperand(1).getReg();
   Register Ins = MI.getOperand(2).getReg();


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