[llvm] aa83bdd - [DAGCombiner][X86] Fold (sub (subcarry X, 0, Carry), Y) -> (subcarry X, Y, Carry)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 8 23:24:53 PDT 2022
Author: Craig Topper
Date: 2022-09-08T22:56:46-07:00
New Revision: aa83bdd1982fbf1174d0769a7842a86779041f37
URL: https://github.com/llvm/llvm-project/commit/aa83bdd1982fbf1174d0769a7842a86779041f37
DIFF: https://github.com/llvm/llvm-project/commit/aa83bdd1982fbf1174d0769a7842a86779041f37.diff
LOG: [DAGCombiner][X86] Fold (sub (subcarry X, 0, Carry), Y) -> (subcarry X, Y, Carry)
Fixes PR57576.
Differential Revision: https://reviews.llvm.org/D133471
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/pr57576.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d2640b6eda0fc..c215772449e19 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3753,6 +3753,12 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
}
+ // (sub (subcarry X, 0, Carry), Y) -> (subcarry X, Y, Carry)
+ if (N0.getOpcode() == ISD::SUBCARRY && isNullConstant(N0.getOperand(1)) &&
+ N0.getResNo() == 0 && N0.hasOneUse())
+ return DAG.getNode(ISD::SUBCARRY, DL, N0->getVTList(),
+ N0.getOperand(0), N1, N0.getOperand(2));
+
if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
// (sub Carry, X) -> (addcarry (sub 0, X), 0, Carry)
if (SDValue Carry = getAsCarry(TLI, N0)) {
diff --git a/llvm/test/CodeGen/X86/pr57576.ll b/llvm/test/CodeGen/X86/pr57576.ll
index ecc30f60532c7..b44eaf3c041be 100644
--- a/llvm/test/CodeGen/X86/pr57576.ll
+++ b/llvm/test/CodeGen/X86/pr57576.ll
@@ -6,8 +6,7 @@ define { i64, i64 } @sub(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 nou
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: subq %rdx, %rax
-; CHECK-NEXT: sbbq $0, %rsi
-; CHECK-NEXT: subq %rcx, %rsi
+; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: retq
%5 = zext i64 %1 to i128
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