[PATCH] D133417: [RISCV] Added optimization patterns with Zbb extension
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 8 08:57:14 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/minu_xori.ll:5
+
+define i1 @test(i64 %c, i64 %a, i64 %b) {
+entry:
----------------
The DAG for this before isel looks like
```
SelectionDAG has 16 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %0
t4: i64,ch = CopyFromReg t0, Register:i64 %1
t22: i64 = setcc t4, t2, setult:ch
t6: i64,ch = CopyFromReg t0, Register:i64 %2
t19: i64 = setcc t6, t2, setult:ch
t26: i64 = or t22, t19
t27: i64 = xor t26, Constant:i64<1>
t13: ch,glue = CopyToReg t0, Register:i64 $x10, t27
t14: ch = RISCVISD::RET_FLAG t13, Register:i64 $x10, t13:1
```
There is no AND, the XOR with 1 was already created.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D133417/new/
https://reviews.llvm.org/D133417
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