[PATCH] D133421: [AArch64] break non-temporal loads over 256 into 256-loads and a smaller load

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal marked 7 inline comments as done.
zjaffal added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17825
+  SmallVector<SDValue, 4> LoadOps;
+  if (MemVT.getSizeInBits() <= 256 || MemVT.getSizeInBits() % 256 == 0 ||
+      256 % MemVT.getScalarSizeInBits() != 0)
----------------
fhahn wrote:
> We should also only do this for non-temporal loads.
Checks are added now for non-temporal loads


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17836
+    SDValue NewPtr =
+        DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(PtrOffset), DL, Flags);
+    Align NewAlign = commonAlignment(LD->getAlign(), PtrOffset);
----------------
fhahn wrote:
> I don't think that's correct, you are passing the offset in bits, but I think it should be in bytes.
> 
> Looking at some of the test changes, the offsets of the loads are wrong, e.g. ` ldnp q0, q2, [x0, #256]`.
This should be fixed now


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133421/new/

https://reviews.llvm.org/D133421