[PATCH] D133421: [AArch64] break non-temporal loads over 256 into 256-loads and a smaller load

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17829
+
+  unsigned PtrOffset = 256;
+  MVT NewVT =
----------------
fhahn wrote:
> Could you add a comment here illustrating what kind of DAG nodes we create to replace the original load?
> 
> 
> It would also be good to document the motivation for special handling for non-temporal loads here.
Would the motivation for the special handling for non-temporal loads be something like: 
We have 256-bit non-temporal load so it might be good to utilise them when having large load instructions? 


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17867
+  SDValue ExtendedReminingLoad = DAG.getNode(
+      ISD::INSERT_SUBVECTOR, DL, NewVT, {NullVector, RemainingLoad, InsertIdx});
+  LoadOps.push_back(ExtendedReminingLoad);
----------------
fhahn wrote:
> Do you need to create `NullVector` explicitly here? Could you just use `DAG.degUNDEF(NewVT)` here?
Yes I will do that


Repository:
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  https://reviews.llvm.org/D133421/new/

https://reviews.llvm.org/D133421