[llvm] e428baf - [LLVM][ARM] Remove options for armv2, 2A, 3 and 3M
David Spickett via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 8 02:50:03 PDT 2022
Author: David Spickett
Date: 2022-09-08T09:49:48Z
New Revision: e428baf0019e5292d943a8e37bf08f1192a1870c
URL: https://github.com/llvm/llvm-project/commit/e428baf0019e5292d943a8e37bf08f1192a1870c
DIFF: https://github.com/llvm/llvm-project/commit/e428baf0019e5292d943a8e37bf08f1192a1870c.diff
LOG: [LLVM][ARM] Remove options for armv2, 2A, 3 and 3M
Fixes #57486
These pre v4 architectures are not specifically supported
by codegen. As demonstrated in the linked issue.
GCC has not supported 3M since GCC 9 and presumably
2 and 2A earlier than that. So we are aligned in that sense.
(see https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2abd6e34fcf3bd9f9ffafcaa47cdc3ed443f9add)
This removes the options and associated testing.
The Pre_v4 build attribute remains mainly because its absence
would be more confusing. It will not be used other than to
complete the list of build attributes as shown in the ABI.
https://github.com/ARM-software/abi-aa/blob/main/addenda32/addenda32.rst#3352the-target-related-attributes
Reviewed By: nickdesaulniers, peter.smith, rengolin
Differential Revision: https://reviews.llvm.org/D133109
Added:
Modified:
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
llvm/test/MC/ARM/directive-arch-armv2.s
llvm/test/MC/ARM/directive-arch-armv2a.s
llvm/test/MC/ARM/directive-arch-armv3.s
llvm/test/MC/ARM/directive-arch-armv3m.s
################################################################################
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 425135d746b99..5bd812aca97f4 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -284,6 +284,10 @@ DWARF Support in Clang
Arm and AArch64 Support in Clang
--------------------------------
+- `-march` values for targeting armv2, armv2A, armv3 and armv3M have been removed.
+ Their presence gave the impression that Clang can correctly generate code for
+ them, which it cannot.
+
Floating Point Support in Clang
-------------------------------
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 7660f3059c531..b5592aae0af5f 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -82,6 +82,10 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--------------------------
+* Support for targeting armv2, armv2A, armv3 and armv3M has been removed.
+ LLVM did not, and was not ever likely to generate correct code for those
+ architecture versions so their presence was misleading.
+
Changes to the AVR Backend
--------------------------
diff --git a/llvm/include/llvm/Support/ARMTargetParser.def b/llvm/include/llvm/Support/ARMTargetParser.def
index 645c3b8963f54..ad498047b0885 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.def
+++ b/llvm/include/llvm/Support/ARMTargetParser.def
@@ -47,14 +47,6 @@ ARM_FPU("softvfp", FK_SOFTVFP, FPUVersion::NONE, NeonSupportLevel::None, FPURest
#endif
ARM_ARCH("invalid", INVALID, "", "",
ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv2", ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4,
- FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv2a", ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4,
- FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv3", ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4,
- FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv3m", ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4,
- FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv4", ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4,
FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv4t", ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T,
diff --git a/llvm/lib/Support/ARMTargetParser.cpp b/llvm/lib/Support/ARMTargetParser.cpp
index d7294b5b10744..e4c6bcb028acb 100644
--- a/llvm/lib/Support/ARMTargetParser.cpp
+++ b/llvm/lib/Support/ARMTargetParser.cpp
@@ -39,12 +39,6 @@ ARM::ArchKind ARM::parseArch(StringRef Arch) {
unsigned ARM::parseArchVersion(StringRef Arch) {
Arch = getCanonicalArchName(Arch);
switch (parseArch(Arch)) {
- case ArchKind::ARMV2:
- case ArchKind::ARMV2A:
- return 2;
- case ArchKind::ARMV3:
- case ArchKind::ARMV3M:
- return 3;
case ArchKind::ARMV4:
case ArchKind::ARMV4T:
return 4;
@@ -125,10 +119,6 @@ ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
case ArchKind::ARMV9_2A:
case ArchKind::ARMV9_3A:
return ProfileKind::A;
- case ArchKind::ARMV2:
- case ArchKind::ARMV2A:
- case ArchKind::ARMV3:
- case ArchKind::ARMV3M:
case ArchKind::ARMV4:
case ArchKind::ARMV4T:
case ArchKind::ARMV5T:
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 4da91e1166cbe..2fe3db2b7f632 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -856,14 +856,6 @@ class ProcNoItin<string Name, list<SubtargetFeature> Features>
// ARM architectures
//
-def ARMv2 : Architecture<"armv2", "ARMv2", []>;
-
-def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
-
-def ARMv3 : Architecture<"armv3", "ARMv3", []>;
-
-def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
-
def ARMv4 : Architecture<"armv4", "ARMv4", []>;
def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 460ec62d5a33e..e75660a1d8a06 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -94,10 +94,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
RClass
};
enum ARMArchEnum {
- ARMv2,
- ARMv2a,
- ARMv3,
- ARMv3m,
ARMv4,
ARMv4t,
ARMv5,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index 15188e0d59d71..386e84c17ae67 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -836,10 +836,6 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
S.setAttributeItem(CPU_arch, ARM::getArchAttr(EmittedArch), false);
switch (Arch) {
- case ARM::ArchKind::ARMV2:
- case ARM::ArchKind::ARMV2A:
- case ARM::ArchKind::ARMV3:
- case ARM::ArchKind::ARMV3M:
case ARM::ArchKind::ARMV4:
S.setAttributeItem(ARM_ISA_use, Allowed, false);
break;
diff --git a/llvm/test/MC/ARM/directive-arch-armv2.s b/llvm/test/MC/ARM/directive-arch-armv2.s
deleted file mode 100644
index f4edc34a36529..0000000000000
--- a/llvm/test/MC/ARM/directive-arch-armv2.s
+++ /dev/null
@@ -1,30 +0,0 @@
-@ Test the .arch directive for armv2
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv2 architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN: | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN: | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
- .syntax unified
- .arch armv2
-
-@ CHECK-ASM: .arch armv2
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_name
-@ CHECK-ATTR: Value: 2
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: Pre-v4
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: ARM_ISA_use
-@ CHECK-ATTR: Description: Permitted
-@ CHECK-ATTR: }
-@ CHECK-ATTR: }
-
diff --git a/llvm/test/MC/ARM/directive-arch-armv2a.s b/llvm/test/MC/ARM/directive-arch-armv2a.s
deleted file mode 100644
index f63f1a57cb9e5..0000000000000
--- a/llvm/test/MC/ARM/directive-arch-armv2a.s
+++ /dev/null
@@ -1,30 +0,0 @@
-@ Test the .arch directive for armv2a
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv2a architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN: | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN: | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
- .syntax unified
- .arch armv2a
-
-@ CHECK-ASM: .arch armv2a
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_name
-@ CHECK-ATTR: Value: 2A
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: Pre-v4
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: ARM_ISA_use
-@ CHECK-ATTR: Description: Permitted
-@ CHECK-ATTR: }
-@ CHECK-ATTR: }
-
diff --git a/llvm/test/MC/ARM/directive-arch-armv3.s b/llvm/test/MC/ARM/directive-arch-armv3.s
deleted file mode 100644
index 001b30ad6bfc0..0000000000000
--- a/llvm/test/MC/ARM/directive-arch-armv3.s
+++ /dev/null
@@ -1,30 +0,0 @@
-@ Test the .arch directive for armv3
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv3 architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN: | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN: | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
- .syntax unified
- .arch armv3
-
-@ CHECK-ASM: .arch armv3
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_name
-@ CHECK-ATTR: Value: 3
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: Pre-v4
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: ARM_ISA_use
-@ CHECK-ATTR: Description: Permitted
-@ CHECK-ATTR: }
-@ CHECK-ATTR: }
-
diff --git a/llvm/test/MC/ARM/directive-arch-armv3m.s b/llvm/test/MC/ARM/directive-arch-armv3m.s
deleted file mode 100644
index 544445e75c473..0000000000000
--- a/llvm/test/MC/ARM/directive-arch-armv3m.s
+++ /dev/null
@@ -1,30 +0,0 @@
-@ Test the .arch directive for armv3m
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv3m architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN: | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN: | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
- .syntax unified
- .arch armv3m
-
-@ CHECK-ASM: .arch armv3m
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_name
-@ CHECK-ATTR: Value: 3M
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: Pre-v4
-@ CHECK-ATTR: }
-@ CHECK-ATTR: Attribute {
-@ CHECK-ATTR: TagName: ARM_ISA_use
-@ CHECK-ATTR: Description: Permitted
-@ CHECK-ATTR: }
-@ CHECK-ATTR: }
-
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index a7dd672d92a4f..8d8327e3b0145 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -20,21 +20,20 @@ using namespace llvm;
namespace {
const char *ARMArch[] = {
- "armv2", "armv2a", "armv3", "armv3m", "armv4",
- "armv4t", "armv5", "armv5t", "armv5e", "armv5te",
- "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl",
- "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m",
- "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7",
- "armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r",
- "armv7r", "armv7-m", "armv7m", "armv7k", "armv7s",
- "armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a",
- "armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a",
- "armv8.3-a", "armv8.3a", "armv8.4-a", "armv8.4a", "armv8.5-a",
- "armv8.5a", "armv8.6-a", "armv8.6a", "armv8.7-a", "armv8.7a",
- "armv8.8-a", "armv8.8a", "armv8-r", "armv8r", "armv8-m.base",
- "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2",
- "xscale", "armv8.1-m.main", "armv9-a", "armv9", "armv9a",
- "armv9.1-a", "armv9.1a", "armv9.2-a", "armv9.2a",
+ "armv4", "armv4t", "armv5", "armv5t", "armv5e",
+ "armv5te", "armv5tej", "armv6", "armv6j", "armv6k",
+ "armv6hl", "armv6t2", "armv6kz", "armv6z", "armv6zk",
+ "armv6-m", "armv6m", "armv6sm", "armv6s-m", "armv7-a",
+ "armv7", "armv7a", "armv7ve", "armv7hl", "armv7l",
+ "armv7-r", "armv7r", "armv7-m", "armv7m", "armv7k",
+ "armv7s", "armv7e-m", "armv7em", "armv8-a", "armv8",
+ "armv8a", "armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a",
+ "armv8.2a", "armv8.3-a", "armv8.3a", "armv8.4-a", "armv8.4a",
+ "armv8.5-a", "armv8.5a", "armv8.6-a", "armv8.6a", "armv8.7-a",
+ "armv8.7a", "armv8.8-a", "armv8.8a", "armv8-r", "armv8r",
+ "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt",
+ "iwmmxt2", "xscale", "armv8.1-m.main", "armv9-a", "armv9",
+ "armv9a", "armv9.1-a", "armv9.1a", "armv9.2-a", "armv9.2a",
};
template <ARM::ISAKind ISAKind>
@@ -438,14 +437,6 @@ bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
}
TEST(TargetParserTest, testARMArch) {
- EXPECT_TRUE(
- testARMArch("armv2", "generic", "v2", ARMBuildAttrs::CPUArch::Pre_v4));
- EXPECT_TRUE(
- testARMArch("armv2a", "generic", "v2a", ARMBuildAttrs::CPUArch::Pre_v4));
- EXPECT_TRUE(
- testARMArch("armv3", "generic", "v3", ARMBuildAttrs::CPUArch::Pre_v4));
- EXPECT_TRUE(
- testARMArch("armv3m", "generic", "v3m", ARMBuildAttrs::CPUArch::Pre_v4));
EXPECT_TRUE(
testARMArch("armv4", "strongarm", "v4",
ARMBuildAttrs::CPUArch::v4));
@@ -603,10 +594,6 @@ TEST(TargetParserTest, testARMExtension) {
EXPECT_FALSE(testARMExtension("xscale", ARM::ArchKind::INVALID, "crc"));
EXPECT_FALSE(testARMExtension("swift", ARM::ArchKind::INVALID, "crc"));
- EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV2, "thumb"));
- EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV2A, "thumb"));
- EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV3, "thumb"));
- EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV3M, "thumb"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV4, "dsp"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV4T, "dsp"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV5T, "simd"));
More information about the llvm-commits
mailing list