[PATCH] D133417: [RISCV] Added optimization patterns with Zbb extension

[Ilya Andreev via Phabricator via llvm-commits]

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Patterns were added to substitute comparation and logic operation with min and logic operation.
Pattern.1
 i = a < c
 j = b < c
 res = i or j
changes to:
 m = min(a, b)
 res = m < c

Pattern.2
 i = a >= c
 j = b >= c
 res = i and j // negation of the result from Pattern.1
changes to:
 m = min(a, b)
 tmp = m < c
 res = tmp xor 1

Pattern.2 is simmilar to Pattern.1 except there is no sgeu instruction and result has to be inversed with xor 1.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133417

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/minu.ll
  llvm/test/CodeGen/RISCV/minu_xori.ll


Index: llvm/test/CodeGen/RISCV/minu_xori.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/minu_xori.ll
@@ -0,0 +1,15 @@
+; RUN: llc  -march=riscv64 -mattr=+v,+zbb -O3 < %s \
+; RUN:  | FileCheck %s
+
+
+define i1 @test(i64 %c, i64 %a, i64 %b) {
+entry:
+  %cmp0 = icmp uge i64 %a, %c
+  %cmp1 = icmp uge i64 %b, %c
+  %res = and i1 %cmp0, %cmp1
+; CHECK: minu [[REG1:a[0-9]+]], [[REG1]], [[REG2:a[0-9]+]]
+; CHECK: sltu [[REG0:a[0-9]+]], [[REG1]], [[REG0]]
+; CHECK: xori [[REG0]], [[REG0]], 1
+  ret i1 %res
+}
+
Index: llvm/test/CodeGen/RISCV/minu.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/minu.ll
@@ -0,0 +1,14 @@
+; RUN: llc  -march=riscv64 -mattr=+v,+zbb -O3 < %s \
+; RUN:  | FileCheck %s
+
+
+define i1 @test(i64 %c, i64 %a, i64 %b) {
+entry:
+  %cmp0 = icmp ult i64 %a, %c
+  %cmp1 = icmp ult i64 %b, %c
+  %res = or i1 %cmp0, %cmp1
+; CHECK: minu [[REG1:a[0-9]+]], [[REG1]], [[REG2:a[0-9]+]]
+; CHECK: sltu [[REG0:a[0-9]+]], [[REG1]], [[REG0]]
+  ret i1 %res
+}
+
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -850,6 +850,13 @@
 def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbpOrZbkb]
 
+let Predicates = [HasStdExtZbb] in {
+def : Pat<(or  (setult GPR:$rs1, GPR:$rs3), (setult GPR:$rs2, GPR:$rs3)),
+          (SLTU (MINU GPR:$rs1, GPR:$rs2), GPR:$rs3)>;
+def : Pat<(and  (setuge GPR:$rs1, GPR:$rs3), (setuge GPR:$rs2, GPR:$rs3)),
+          (XORI (SLTU (MINU GPR:$rs1, GPR:$rs2), GPR:$rs3), 1)>;
+} // Predicates = [HasStdExtZbb]
+
 let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
 def : PatGprGpr<shiftop<rotl>, ROL>;
 def : PatGprGpr<shiftop<rotr>, ROR>;


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