[PATCH] D126809: [ARM64EC 8/?] Implement ARM64EC "thunk" calling conventions

Tue Sep 6 23:21:05 PDT 2022

bcl5980 added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64CallingConvention.td:209
+let Entry = 1 in
+def CC_AArch64_Arm64EC_Thunk : CallingConv<[
+  // Byval aggregates are passed by pointer
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efriedma wrote:
> bcl5980 wrote:
> > Do we need to add CSR for the callingconv also in this change? 
> > `D6`, `D7` should be non-volatile on x64. 
> CSRs are listed elsewhere... but yes, we do need to mess with AArch64RegisterInfo::getCalleeSavedRegs to make entry thunks correctly save the registers.
If we consider entry thunk, we need to save q6-q15 instead of d8-d15. Even through MS still hasn't documented the unwind code `save_qregp`, we may need to add (sequence "Q%u", 6, 15) into something like CSR_AArch64_Arm64EC_Thunk.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126809/new/

https://reviews.llvm.org/D126809