[PATCH] D133372: [docs][RISCV] Document status of Zicpo(m,z,p) extensions

[Philip Reames via Phabricator via llvm-commits]

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Unless I missed something when checking, we only support these in assembly.  Given that, documenting them is a good opportunity to define support levels which will be useful for other extensions as well.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133372

Files:
  llvm/docs/RISCVUsage.rst


Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -74,10 +74,20 @@
      ``Zvl16384b``  Supported
      ``Zvl32768b``  Supported
      ``Zvl65536b``  Supported
+     ``Zicbom``     Assembly Support
+     ``Zicboz``     Assembly Support
+     ``Zicbop``     Assembly Support
      =============  ========================
 
+Assembly Support
+  LLVM supports the associated instructions in assembly.  All assembly related tools (e.g. assembler, disassembler, llvm-objdump, etc..) are supported.  Compiler and linker will accept extension names, and linked binaries will contain appropriate ELF flags and attributes to reflect use of named extension.
+
+Supported
+  Fully supported by the compiler.  This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions.
+
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
-  LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly tools (e.g. assembler, disassembler, llvm-objdump, etc..) don't have this restriction.
+  LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly support doesn't have this restriction.
+
 
 Specification Documents
 =======================


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