[PATCH] D133063: [docs] Add a RISC-V Usage page

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/docs/RISCVUsage.rst:72
+
+Zve32x, Zve32f, Zvl32b
+  LLVM currently assumes a minimum VLEN (vector register width) of 64 bytes.
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frasercrmck wrote:
> Maybe have these back-ticked for consistency?
Because the table in the spec stopped at 1024, and I skimmed over the "Longer vector length extensions should follow the same pattern. wording.  Will update to add the others.  


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133063/new/

https://reviews.llvm.org/D133063